Lines Matching defs:amd_xgbe_phy_priv
392 struct amd_xgbe_phy_priv { struct
393 struct platform_device *pdev;
394 struct acpi_device *adev;
395 struct device *dev;
397 struct phy_device *phydev;
400 struct resource *rxtx_res;
401 struct resource *sir0_res;
402 struct resource *sir1_res;
405 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
406 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
407 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
409 int an_irq;
410 char an_irq_name[IFNAMSIZ + 32];
411 struct work_struct an_irq_work;
412 unsigned int an_irq_allocated;
414 unsigned int speed_set;
422 u32 serdes_blwc[XGBE_PHY_SPEEDS];
423 u32 serdes_cdr_rate[XGBE_PHY_SPEEDS];
424 u32 serdes_pq_skew[XGBE_PHY_SPEEDS];
425 u32 serdes_tx_amp[XGBE_PHY_SPEEDS];
426 u32 serdes_dfe_tap_cfg[XGBE_PHY_SPEEDS];
427 u32 serdes_dfe_tap_ena[XGBE_PHY_SPEEDS];
430 struct mutex an_mutex;
431 enum amd_xgbe_phy_an an_result;
432 enum amd_xgbe_phy_an an_state;
433 enum amd_xgbe_phy_rx kr_state;
434 enum amd_xgbe_phy_rx kx_state;
435 struct work_struct an_work;
436 struct workqueue_struct *an_workqueue;
437 unsigned int an_supported;
438 unsigned int parallel_detect;
439 unsigned int fec_ability;
440 unsigned long an_start;
442 unsigned int lpm_ctrl; /* CTRL1 for resume */