85 static int clksrc = 0;			/* default is 0(auto) */  variable
86 module_param(clksrc, int, 0);
87 MODULE_PARM_DESC(clksrc, "clock input source selection");
341 		(clksrc>=2) ? ((clksrc==3)?"40MHz XCLK":"48MHz XCLK")  in vlsi_seq_show()
342 			    : ((clksrc==1)?"48MHz PLL":"autodetect"));  in vlsi_seq_show()
768 		nphyctl = PHYCTL_MIR(clksrc==3);  in vlsi_set_baud()
785 				nphyctl = PHYCTL_SIR(baudrate,sirpulse,clksrc==3);  in vlsi_set_baud()
1146 	if (clksrc < 2) { /* auto or PLL: try PLL */  in vlsi_start_clock()
1165 			if (clksrc == 1) { /* explicitly asked for PLL hence bail out */  in vlsi_start_clock()
1173 				clksrc = 3;	/* fallback to 40MHz XCLK (OB800) */  in vlsi_start_clock()
1176 				 __func__, clksrc);  in vlsi_start_clock()
1179 			clksrc = 1;	/* got successful PLL lock */  in vlsi_start_clock()
1182 	if (clksrc != 1) {  in vlsi_start_clock()
1187 		if (clksrc == 3)  in vlsi_start_clock()
1824 	if (clksrc < 0  ||  clksrc > 3) {  in vlsi_mod_init()
1826 				    drivername, clksrc);  in vlsi_mod_init()