244 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,  in WriteRegBit()  function
300 		WriteRegBit(iobase, 0x11, 0, 0);  in SetFIFO()
301 		WriteRegBit(iobase, 0x11, 7, 1);  in SetFIFO()
304 		WriteRegBit(iobase, 0x11, 0, 0);  in SetFIFO()
305 		WriteRegBit(iobase, 0x11, 7, 0);  in SetFIFO()
308 		WriteRegBit(iobase, 0x11, 0, 1);  in SetFIFO()
309 		WriteRegBit(iobase, 0x11, 7, 0);  in SetFIFO()
312 		WriteRegBit(iobase, 0x11, 0, 0);  in SetFIFO()
313 		WriteRegBit(iobase, 0x11, 7, 0);  in SetFIFO()
318 #define CRC16(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_L_0,7,val)	//0 for 32 CRC
325 #define SIRFilter(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_L_0,3,val)
326 #define Filter(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,2,val)
327 #define InvertTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,1,val)
328 #define InvertRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,0,val)
330 #define EnableTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,4,val)
331 #define EnableRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,3,val)
332 #define EnableDMA(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_H_0,2,val)
333 #define SIRRecvAny(BaseAddr,val)    WriteRegBit(BaseAddr,I_CF_H_0,1,val)
334 #define DiableTrans(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_H_0,0,val)
341 #define EnPhys(BaseAddr,val)   WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
351 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val)	//1 disable
352 #define DisablePulseWidthAdjust(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_3,4,val)	//1 disable
353 #define UseOneRX(BaseAddr,val)                  WriteRegBit(BaseAddr,I_CF_3,1,val)	//0 use two RX
354 #define SlowIRRXLowActive(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_3,0,val)	//0 show RX high…
356 #define EnAllInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,7,val)
357 #define TXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,6,val)
358 #define RXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,5,val)
359 #define ClearRXInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,4,val)	// 1 clear
366 #define EnTXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,7,val)
367 #define EnRXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,6,val)
368 #define SwapDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,5,val)
369 #define EnInternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,4,val)
370 #define EnExternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,3,val)
372 #define EnTXFIFOHalfLevelInt(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_1,4,val)	//half empty int (…
373 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
374 #define EnTXFIFOReadyInt(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_1,6,val)	//int when reach i…
376 #define ForceUnderrun(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_2,7,val)	// force an underrun int
377 #define EnTXCRC(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,6,val)	//1 for FIR,MIR...0 (not …
378 #define ForceBADCRC(BaseAddr,val)     WriteRegBit(BaseAddr,TX_CT_2,5,val)	//force an bad CRC
379 #define SendSIP(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,4,val)	//send indication pulse f…
380 #define ClearEnTX(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_2,3,val)	// opposite to EnTX
384 #define EnRXSpecInt(BaseAddr,val)           WriteRegBit(BaseAddr,RX_CT,0,val)
385 #define EnRXFIFOReadyInt(BaseAddr,val)      WriteRegBit(BaseAddr,RX_CT,1,val)	//enable int when rea…
386 #define EnRXFIFOHalfLevelInt(BaseAddr,val)  WriteRegBit(BaseAddr,RX_CT,7,val)	//enable int when (1)…
392 #define EnGPIOtoRX2(BaseAddr,val)	WriteRegBit(BaseAddr,I_CF_4,7,val)
393 #define EnTimerInt(BaseAddr,val)		WriteRegBit(BaseAddr,I_CF_4,1,val)
394 #define ClearTimerInt(BaseAddr,val)	WriteRegBit(BaseAddr,I_CF_4,0,val)
396 #define WriteGIO(BaseAddr,val)	    WriteRegBit(BaseAddr,I_T_C_L,7,val)
399 #define WriteTX(BaseAddr,val)		WriteRegBit(BaseAddr,I_T_C_L,0,val)
401 #define EnRX2(BaseAddr,val)		    WriteRegBit(BaseAddr,I_T_C_H,7,val)
813 	WriteRegBit(BaseAddr, I_CF_H_0, 5, val);  in SetVFIR()
820 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetFIR()
823 	WriteRegBit(BaseAddr, I_CF_L_0, 6, val);  in SetFIR()
830 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetMIR()
833 	WriteRegBit(BaseAddr, I_CF_L_0, 5, val);  in SetMIR()
840 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetSIR()
843 	WriteRegBit(BaseAddr, I_CF_L_0, 4, val);  in SetSIR()