239 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)  in WriteReg()  function
263 	WriteReg(BaseAddr, RegNum, Wtemp);  in WriteRegBit()
287 		WriteReg(iobase, I_CF_L_2, low);  in SetMaxRxPacketSize()
288 		WriteReg(iobase, I_CF_H_2, high);  in SetMaxRxPacketSize()
336 #define SetSIRBOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_BOF,val)
337 #define SetSIREOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_EOF,val)
390 #define SetPacketAddr(BaseAddr,addr)        WriteReg(BaseAddr,P_ADDR,addr)
410 	WriteReg(iobase, TIMER, count);  in SetTimer()
422 		WriteReg(iobase, TX_C_L, low);  in SetSendByte()
423 		WriteReg(iobase, TX_C_H, high);  in SetSendByte()
432 	WriteReg(iobase, RESET, type);  in ResetChip()
534 		WriteReg(iobase, 0x34, bTmp | Clk_bit);  in ActClk()
536 		WriteReg(iobase, 0x34, bTmp & ~Clk_bit);  in ActClk()
550 	WriteReg(iobase, 0x34, bTmp);  in ClkTx()
558 	WriteReg(iobase, 0x34, bTmp);  in ClkTx()
694 	WriteReg(iobase, 0x35, bTmp | 0x40);	// Driver ITMOFF  in SetSITmode()
695 	WriteReg(iobase, 0x28, bTmp | 0x80);	// enable All interrupt  in SetSITmode()
716 	WriteReg(iobase, I_ST_CT_0, 0x00);	// open CHIP on  in InitCard()
742 	WriteReg(iobase, I_ST_CT_0, 0x80);  in CommonInit()
780 	WriteReg(iobase, I_CF_H_1, temp);  in SetBaudRate()
793 	WriteReg(iobase, I_CF_L_1, temp);  in SetPulseWidth()
794 	WriteReg(iobase, I_CF_H_1, temp1);  in SetPulseWidth()
803 	WriteReg(iobase, I_CF_L_1, temp);  in SetSendPreambleCount()
812 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetVFIR()
822 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetFIR()
832 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetMIR()
842 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetSIR()