Lines Matching refs:BaseAddr
234 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum) in ReadReg() argument
236 return (__u8) inb(BaseAddr + iRegNum); in ReadReg()
239 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal) in WriteReg() argument
241 outb(iVal, BaseAddr + iRegNum); in WriteReg()
244 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum, in WriteRegBit() argument
254 Rtemp = ReadReg(BaseAddr, RegNum); in WriteRegBit()
263 WriteReg(BaseAddr, RegNum, Wtemp); in WriteRegBit()
267 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum, in CheckRegBit() argument
277 temp = ReadReg(BaseAddr, RegNum); in CheckRegBit()
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC argument
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val) argument
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val) argument
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val) argument
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val) argument
330 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val) argument
331 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val) argument
332 #define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val) argument
333 #define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val) argument
334 #define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val) argument
336 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val) argument
337 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val) argument
338 #define GetSIRBOF(BaseAddr) ReadReg(BaseAddr,I_SIR_BOF) argument
339 #define GetSIREOF(BaseAddr) ReadReg(BaseAddr,I_SIR_EOF) argument
341 #define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val) argument
342 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO argument
343 #define IsVFIROn(BaseAddr) CheckRegBit(BaseAddr,0x14,0) //RO for VT1211 only argument
344 #define IsFIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO argument
345 #define IsMIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO argument
346 #define IsSIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO argument
347 #define IsEnableTX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO argument
348 #define IsEnableRX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO argument
349 #define Is16CRC(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO argument
351 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable argument
352 #define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable argument
353 #define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX argument
354 #define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high… argument
356 #define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val) argument
357 #define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val) argument
358 #define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val) argument
359 #define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear argument
361 #define IsRXInt(BaseAddr) CheckRegBit(BaseAddr,H_ST,4) argument
362 #define GetIntIndentify(BaseAddr) ((ReadReg(BaseAddr,H_ST)&0xf1) >>1) argument
363 #define IsHostBusy(BaseAddr) CheckRegBit(BaseAddr,H_ST,0) argument
364 #define GetHostStatus(BaseAddr) ReadReg(BaseAddr,H_ST) //RO argument
366 #define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val) argument
367 #define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val) argument
368 #define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val) argument
369 #define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val) argument
370 #define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val) argument
372 #define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (… argument
373 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val) argument
374 #define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach i… argument
376 #define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int argument
377 #define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not … argument
378 #define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC argument
379 #define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse f… argument
380 #define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX argument
382 #define GetTXStatus(BaseAddr) ReadReg(BaseAddr,TX_ST) //RO argument
384 #define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val) argument
385 #define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when rea… argument
386 #define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1)… argument
388 #define GetRXStatus(BaseAddr) ReadReg(BaseAddr,RX_ST) //RO argument
390 #define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr) argument
392 #define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val) argument
393 #define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val) argument
394 #define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val) argument
396 #define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val) argument
397 #define ReadGIO(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,7) argument
398 #define ReadRX(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,3) //RO argument
399 #define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val) argument
401 #define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val) argument
402 #define ReadRX2(BaseAddr) CheckRegBit(BaseAddr,I_T_C_H,7) argument
404 #define GetFIRVersion(BaseAddr) ReadReg(BaseAddr,VERSION) argument
807 static void SetVFIR(__u16 BaseAddr, __u8 val) in SetVFIR() argument
811 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetVFIR()
812 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetVFIR()
813 WriteRegBit(BaseAddr, I_CF_H_0, 5, val); in SetVFIR()
816 static void SetFIR(__u16 BaseAddr, __u8 val) in SetFIR() argument
820 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0); in SetFIR()
821 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetFIR()
822 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetFIR()
823 WriteRegBit(BaseAddr, I_CF_L_0, 6, val); in SetFIR()
826 static void SetMIR(__u16 BaseAddr, __u8 val) in SetMIR() argument
830 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0); in SetMIR()
831 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetMIR()
832 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetMIR()
833 WriteRegBit(BaseAddr, I_CF_L_0, 5, val); in SetMIR()
836 static void SetSIR(__u16 BaseAddr, __u8 val) in SetSIR() argument
840 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0); in SetSIR()
841 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetSIR()
842 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetSIR()
843 WriteRegBit(BaseAddr, I_CF_L_0, 4, val); in SetSIR()