Lines Matching refs:inb
362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), in register_bank()
659 high = inb(fir_base + IRCC_ID_HIGH); in smsc_ircc_present()
660 low = inb(fir_base + IRCC_ID_LOW); in smsc_ircc_present()
661 chip = inb(fir_base + IRCC_CHIP_ID); in smsc_ircc_present()
662 version = inb(fir_base + IRCC_VERSION); in smsc_ircc_present()
663 config = inb(fir_base + IRCC_INTERFACE); in smsc_ircc_present()
699 config = inb(fir_base + IRCC_INTERFACE); in smsc_ircc_setup_io()
762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), in smsc_ircc_init_chip()
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), in smsc_ircc_init_chip()
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), in smsc_ircc_init_chip()
772 (void) inb(iobase + IRCC_FIFO_THRESHOLD); in smsc_ircc_init_chip()
776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); in smsc_ircc_init_chip()
981 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); in smsc_ircc_set_fir_speed()
985 …outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + … in smsc_ircc_set_fir_speed()
988 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); in smsc_ircc_set_fir_speed()
1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); in smsc_ircc_fir_start()
1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), in smsc_ircc_fir_start()
1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), in smsc_ircc_fir_start()
1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); in smsc_ircc_fir_start()
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); in smsc_ircc_fir_stop()
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit()
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; in smsc_ircc_dma_xmit()
1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_xmit()
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit_complete()
1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { in smsc_ircc_dma_xmit_complete()
1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_receive()
1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); in smsc_ircc_dma_receive_complete()
1424 lsr= inb(iobase + IRCC_LSR); in smsc_ircc_dma_receive_complete()
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; in smsc_ircc_dma_receive_complete()
1493 inb(iobase + UART_RX)); in smsc_ircc_sir_receive()
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR); in smsc_ircc_sir_receive()
1529 iir = inb(iobase + IRCC_IIR); in smsc_ircc_interrupt()
1536 lcra = inb(iobase + IRCC_LCR_A); in smsc_ircc_interrupt()
1537 lsr = inb(iobase + IRCC_LSR); in smsc_ircc_interrupt()
1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1587 lsr = inb(iobase + UART_LSR); in smsc_ircc_interrupt_sir()
1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1919 …outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A)… in smsc_ircc_sir_start()
2024 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { in smsc_ircc_sir_write()
2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) in smsc_ircc_sir_wait_hw_transmitter_finish()
2193 mode = inb(cfgbase + 1); in smsc_superio_flat()
2201 sirbase = inb(cfgbase + 1) << 2; in smsc_superio_flat()
2205 firbase = inb(cfgbase + 1) << 3; in smsc_superio_flat()
2209 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; in smsc_superio_flat()
2213 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; in smsc_superio_flat()
2249 sir_io = inb(cfg_base + 1) << 8; in smsc_superio_paged()
2251 sir_io |= inb(cfg_base + 1); in smsc_superio_paged()
2255 fir_io = inb(cfg_base + 1) << 8; in smsc_superio_paged()
2257 fir_io |= inb(cfg_base + 1); in smsc_superio_paged()
2275 return inb(cfg_base) != reg ? -1 : 0; in smsc_access()
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ in smsc_ircc_probe()
2293 xdevid = inb(cfg_base + 1); in smsc_ircc_probe()
2309 devid = inb(cfg_base + 1); in smsc_ircc_probe()
2319 rev = inb(cfg_base + 1); in smsc_ircc_probe()
2536 tmpbyte = inb(iobase +1); // Read device ID in preconfigure_smsc_chip()
2545 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2554 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2558 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; in preconfigure_smsc_chip()
2567 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2576 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; in preconfigure_smsc_chip()
2583 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2589 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2594 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2598 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2602 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2924 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, in smsc_ircc_set_transceiver_smsc_ircc_atc()
2927 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && in smsc_ircc_set_transceiver_smsc_ircc_atc()
2933 __func__, inb(fir_base + IRCC_ATC)); in smsc_ircc_set_transceiver_smsc_ircc_atc()
2970 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); in smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select()
3009 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); in smsc_ircc_set_transceiver_toshiba_sat1800()