100 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)  in write_short_reg()  function
357 	write_short_reg(devrec, REG_TXNCON, val);  in mrf24j40_tx()
406 	write_short_reg(devrec, REG_INTCON, val);  in mrf24j40_start()
423 	write_short_reg(devrec, REG_INTCON, val);  in mrf24j40_stop()
447 	write_short_reg(devrec, REG_RFCTL, val);  in mrf24j40_set_channel()
449 	write_short_reg(devrec, REG_RFCTL, val);  in mrf24j40_set_channel()
471 		write_short_reg(devrec, REG_SADRH, addrh);  in mrf24j40_filter()
472 		write_short_reg(devrec, REG_SADRL, addrl);  in mrf24j40_filter()
483 			write_short_reg(devrec, REG_EADR0 + i, addr[i]);  in mrf24j40_filter()
499 		write_short_reg(devrec, REG_PANIDH, panidh);  in mrf24j40_filter()
500 		write_short_reg(devrec, REG_PANIDL, panidl);  in mrf24j40_filter()
517 		write_short_reg(devrec, REG_RXMCR, val);  in mrf24j40_filter()
544 	write_short_reg(devrec, REG_BBREG1, val);  in mrf24j40_handle_rx()
576 	write_short_reg(devrec, REG_BBREG1, val);  in mrf24j40_handle_rx()
621 	ret = write_short_reg(devrec, REG_SOFTRST, 0x07);  in mrf24j40_hw_init()
625 	ret = write_short_reg(devrec, REG_PACON2, 0x98);  in mrf24j40_hw_init()
629 	ret = write_short_reg(devrec, REG_TXSTBL, 0x95);  in mrf24j40_hw_init()
661 	ret = write_short_reg(devrec, REG_BBREG2, 0x80);  in mrf24j40_hw_init()
665 	ret = write_short_reg(devrec, REG_CCAEDTH, 0x60);  in mrf24j40_hw_init()
669 	ret = write_short_reg(devrec, REG_BBREG6, 0x40);  in mrf24j40_hw_init()
673 	ret = write_short_reg(devrec, REG_RFCTL, 0x04);  in mrf24j40_hw_init()
677 	ret = write_short_reg(devrec, REG_RFCTL, 0x0);  in mrf24j40_hw_init()
690 	ret = write_short_reg(devrec, REG_RXMCR, val);  in mrf24j40_hw_init()
704 		write_short_reg(devrec, REG_TRISGPIO, val);  in mrf24j40_hw_init()
708 		write_short_reg(devrec, REG_GPIO, val);  in mrf24j40_hw_init()