150 	rrpriv->regs = pci_iomap(pdev, 0, 0x1000);  in rr_init_one()
151 	if (!rrpriv->regs) {  in rr_init_one()
189 	writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,  in rr_init_one()
190 		&rrpriv->regs->HostCtrl);  in rr_init_one()
213 	if (rrpriv->regs)  in rr_init_one()
214 		pci_iounmap(pdev, rrpriv->regs);  in rr_init_one()
228 	if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) {  in rr_remove_one()
231 		writel(HALT_NIC, &rr->regs->HostCtrl);  in rr_remove_one()
241 	pci_iounmap(pdev, rr->regs);  in rr_remove_one()
254 	struct rr_regs __iomem *regs;  in rr_issue_cmd()  local
257 	regs = rrpriv->regs;  in rr_issue_cmd()
262 	if (readl(&regs->HostCtrl) & NIC_HALTED){  in rr_issue_cmd()
264 		       "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));  in rr_issue_cmd()
265 		if (readl(&regs->Mode) & FATAL_ERR)  in rr_issue_cmd()
267 			       readl(&regs->Fail1), readl(&regs->Fail2));  in rr_issue_cmd()
272 	writel(*(u32*)(cmd), &regs->CmdRing[idx]);  in rr_issue_cmd()
279 	if (readl(&regs->Mode) & FATAL_ERR)  in rr_issue_cmd()
280 		printk("error code %02x\n", readl(&regs->Fail1));  in rr_issue_cmd()
291 	struct rr_regs __iomem *regs;  in rr_reset()  local
296 	regs = rrpriv->regs;  in rr_reset()
300 	writel(0x01000000, &regs->TX_state);  in rr_reset()
301 	writel(0xff800000, &regs->RX_state);  in rr_reset()
302 	writel(0, &regs->AssistState);  in rr_reset()
303 	writel(CLEAR_INTA, &regs->LocalCtrl);  in rr_reset()
304 	writel(0x01, &regs->BrkPt);  in rr_reset()
305 	writel(0, &regs->Timer);  in rr_reset()
306 	writel(0, &regs->TimerRef);  in rr_reset()
307 	writel(RESET_DMA, &regs->DmaReadState);  in rr_reset()
308 	writel(RESET_DMA, &regs->DmaWriteState);  in rr_reset()
309 	writel(0, &regs->DmaWriteHostHi);  in rr_reset()
310 	writel(0, &regs->DmaWriteHostLo);  in rr_reset()
311 	writel(0, &regs->DmaReadHostHi);  in rr_reset()
312 	writel(0, &regs->DmaReadHostLo);  in rr_reset()
313 	writel(0, &regs->DmaReadLen);  in rr_reset()
314 	writel(0, &regs->DmaWriteLen);  in rr_reset()
315 	writel(0, &regs->DmaWriteLcl);  in rr_reset()
316 	writel(0, &regs->DmaWriteIPchecksum);  in rr_reset()
317 	writel(0, &regs->DmaReadLcl);  in rr_reset()
318 	writel(0, &regs->DmaReadIPchecksum);  in rr_reset()
319 	writel(0, &regs->PciState);  in rr_reset()
321 	writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);  in rr_reset()
323 	writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);  in rr_reset()
325 	writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);  in rr_reset()
332 	writel(0xdf000, &regs->RxBase);  in rr_reset()
333 	writel(0xdf000, &regs->RxPrd);  in rr_reset()
334 	writel(0xdf000, &regs->RxCon);  in rr_reset()
335 	writel(0xce000, &regs->TxBase);  in rr_reset()
336 	writel(0xce000, &regs->TxPrd);  in rr_reset()
337 	writel(0xce000, &regs->TxCon);  in rr_reset()
338 	writel(0, &regs->RxIndPro);  in rr_reset()
339 	writel(0, &regs->RxIndCon);  in rr_reset()
340 	writel(0, &regs->RxIndRef);  in rr_reset()
341 	writel(0, &regs->TxIndPro);  in rr_reset()
342 	writel(0, &regs->TxIndCon);  in rr_reset()
343 	writel(0, &regs->TxIndRef);  in rr_reset()
344 	writel(0xcc000, &regs->pad10[0]);  in rr_reset()
345 	writel(0, &regs->DrCmndPro);  in rr_reset()
346 	writel(0, &regs->DrCmndCon);  in rr_reset()
347 	writel(0, &regs->DwCmndPro);  in rr_reset()
348 	writel(0, &regs->DwCmndCon);  in rr_reset()
349 	writel(0, &regs->DwCmndRef);  in rr_reset()
350 	writel(0, &regs->DrDataPro);  in rr_reset()
351 	writel(0, &regs->DrDataCon);  in rr_reset()
352 	writel(0, &regs->DrDataRef);  in rr_reset()
353 	writel(0, &regs->DwDataPro);  in rr_reset()
354 	writel(0, &regs->DwDataCon);  in rr_reset()
355 	writel(0, &regs->DwDataRef);  in rr_reset()
358 	writel(0xffffffff, &regs->MbEvent);  in rr_reset()
359 	writel(0, &regs->Event);  in rr_reset()
361 	writel(0, &regs->TxPi);  in rr_reset()
362 	writel(0, &regs->IpRxPi);  in rr_reset()
364 	writel(0, &regs->EvtCon);  in rr_reset()
365 	writel(0, &regs->EvtPrd);  in rr_reset()
370 		writel(0, &regs->CmdRing[i]);  in rr_reset()
375 	writel(RBURST_64|WBURST_64, &regs->PciState);  in rr_reset()
386 	writel(start_pc + 0x800, &regs->Pc);  in rr_reset()
390 	writel(start_pc, &regs->Pc);  in rr_reset()
405 	struct rr_regs __iomem *regs = rrpriv->regs;  in rr_read_eeprom()  local
408 	io = readl(&regs->ExtIo);  in rr_read_eeprom()
409 	writel(0, &regs->ExtIo);  in rr_read_eeprom()
410 	misc = readl(&regs->LocalCtrl);  in rr_read_eeprom()
411 	writel(0, &regs->LocalCtrl);  in rr_read_eeprom()
412 	host = readl(&regs->HostCtrl);  in rr_read_eeprom()
413 	writel(host | HALT_NIC, &regs->HostCtrl);  in rr_read_eeprom()
417 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);  in rr_read_eeprom()
419 		buf[i] = (readl(&regs->WinData) >> 24) & 0xff;  in rr_read_eeprom()
423 	writel(host, &regs->HostCtrl);  in rr_read_eeprom()
424 	writel(misc, &regs->LocalCtrl);  in rr_read_eeprom()
425 	writel(io, &regs->ExtIo);  in rr_read_eeprom()
457 	struct rr_regs __iomem *regs = rrpriv->regs;  in write_eeprom()  local
460 	io = readl(&regs->ExtIo);  in write_eeprom()
461 	writel(0, &regs->ExtIo);  in write_eeprom()
462 	misc = readl(&regs->LocalCtrl);  in write_eeprom()
463 	writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);  in write_eeprom()
467 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);  in write_eeprom()
474 		if ((readl(&regs->WinData) & 0xff000000) != data){  in write_eeprom()
475 			writel(data, &regs->WinData);  in write_eeprom()
481 				if ((readl(&regs->WinData) & 0xff000000) ==  in write_eeprom()
488 					       readl(&regs->WinData));  in write_eeprom()
496 	writel(misc, &regs->LocalCtrl);  in write_eeprom()
497 	writel(io, &regs->ExtIo);  in write_eeprom()
507 	struct rr_regs __iomem *regs;  in rr_init()  local
511 	regs = rrpriv->regs;  in rr_init()
513 	rev = readl(&regs->FwRev);  in rr_init()
529 	printk("  Maximum receive rings %i\n", readl(&regs->MaxRxRng));  in rr_init()
558 	struct rr_regs __iomem *regs;  in rr_init1()  local
566 	regs = rrpriv->regs;  in rr_init1()
570 	hostctrl = readl(&regs->HostCtrl);  in rr_init1()
571 	writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);  in rr_init1()
582 	set_rxaddr(regs, rrpriv->rx_ctrl_dma);  in rr_init1()
583 	set_infoaddr(regs, rrpriv->info_dma);  in rr_init1()
597 		writel(0, &regs->CmdRing[i]);  in rr_init1()
624 	writel(0x5000, &regs->ConRetry);  in rr_init1()
625 	writel(0x100, &regs->ConRetryTmr);  in rr_init1()
626 	writel(0x500000, &regs->ConTmout);  in rr_init1()
627  	writel(0x60, &regs->IntrTmr);  in rr_init1()
628 	writel(0x500000, &regs->TxDataMvTimeout);  in rr_init1()
629 	writel(0x200000, &regs->RxDataMvTimeout);  in rr_init1()
630  	writel(0x80, &regs->WriteDmaThresh);  in rr_init1()
631  	writel(0x80, &regs->ReadDmaThresh);  in rr_init1()
637 	writel(hostctrl, &regs->HostCtrl);  in rr_init1()
728 	struct rr_regs __iomem *regs;  in rr_handle_event()  local
732 	regs = rrpriv->regs;  in rr_handle_event()
737 			tmp = readl(&regs->FwRev);  in rr_handle_event()
742 			writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);  in rr_handle_event()
762 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
763 			       &regs->HostCtrl);  in rr_handle_event()
769 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
770 			       &regs->HostCtrl);  in rr_handle_event()
793 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
794 			       &regs->HostCtrl);  in rr_handle_event()
805 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
806 			       &regs->HostCtrl);  in rr_handle_event()
812 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
813 			       &regs->HostCtrl);  in rr_handle_event()
819 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
820 			       &regs->HostCtrl);  in rr_handle_event()
826 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
827 			       &regs->HostCtrl);  in rr_handle_event()
880 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
881 			       &regs->HostCtrl);  in rr_handle_event()
887 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
888 			       &regs->HostCtrl);  in rr_handle_event()
894 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
895 			       &regs->HostCtrl);  in rr_handle_event()
931 	struct rr_regs __iomem *regs = rrpriv->regs;  in rx_int()  local
1011 			writel(index, &regs->IpRxPi);  in rx_int()
1024 	struct rr_regs __iomem *regs;  in rr_interrupt()  local
1029 	regs = rrpriv->regs;  in rr_interrupt()
1031 	if (!(readl(&regs->HostCtrl) & RR_INT))  in rr_interrupt()
1036 	prodidx = readl(&regs->EvtPrd);  in rr_interrupt()
1099 	writel(eidx, &regs->EvtCon);  in rr_interrupt()
1153 	struct rr_regs __iomem *regs = rrpriv->regs;  in rr_timer()  local
1156 	if (readl(&regs->HostCtrl) & NIC_HALTED){  in rr_timer()
1167 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_timer()
1168 			       &regs->HostCtrl);  in rr_timer()
1181 	struct rr_regs __iomem *regs;  in rr_open()  local
1186 	regs = rrpriv->regs;  in rr_open()
1216 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);  in rr_open()
1217 	readl(&regs->HostCtrl);  in rr_open()
1244 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);  in rr_open()
1267 	struct rr_regs __iomem *regs;  in rr_dump()  local
1273 	regs = rrpriv->regs;  in rr_dump()
1278 	       readl(&regs->RxPrd), readl(&regs->TxPrd),  in rr_dump()
1279 	       readl(&regs->EvtPrd), readl(&regs->TxPi),  in rr_dump()
1282 	printk("Error code 0x%x\n", readl(&regs->Fail1));  in rr_dump()
1284 	index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;  in rr_dump()
1330 	struct rr_regs __iomem *regs = rrpriv->regs;  in rr_close()  local
1345 	tmp = readl(&regs->HostCtrl);  in rr_close()
1351 		writel(tmp, &regs->HostCtrl);  in rr_close()
1352 		readl(&regs->HostCtrl);  in rr_close()
1359 	writel(0, &regs->TxPi);  in rr_close()
1360 	writel(0, &regs->IpRxPi);  in rr_close()
1362 	writel(0, &regs->EvtCon);  in rr_close()
1363 	writel(0, &regs->EvtPrd);  in rr_close()
1366 		writel(0, &regs->CmdRing[i]);  in rr_close()
1395 	struct rr_regs __iomem *regs = rrpriv->regs;  in rr_start_xmit()  local
1403 	if (readl(&regs->Mode) & FATAL_ERR)  in rr_start_xmit()
1405 		       readl(&regs->Fail1), readl(&regs->Fail2));  in rr_start_xmit()
1447 	writel(txctrl->pi, &regs->TxPi);  in rr_start_xmit()
1470 	struct rr_regs __iomem *regs;  in rr_load_firmware()  local
1477 	regs = rrpriv->regs;  in rr_load_firmware()
1482 	if (!(readl(&regs->HostCtrl) & NIC_HALTED)){  in rr_load_firmware()
1488 	localctrl = readl(&regs->LocalCtrl);  in rr_load_firmware()
1489 	writel(0, &regs->LocalCtrl);  in rr_load_firmware()
1491 	writel(0, &regs->EvtPrd);  in rr_load_firmware()
1492 	writel(0, &regs->RxPrd);  in rr_load_firmware()
1493 	writel(0, &regs->TxPrd);  in rr_load_firmware()
1500 	io = readl(&regs->ExtIo);  in rr_load_firmware()
1501 	writel(0, &regs->ExtIo);  in rr_load_firmware()
1505 		writel(i * 4, &regs->WinBase);  in rr_load_firmware()
1507 		writel(0, &regs->WinData);  in rr_load_firmware()
1510 	writel(io, &regs->ExtIo);  in rr_load_firmware()
1556 			writel(sptr, &regs->WinBase);  in rr_load_firmware()
1558 			writel(tmp, &regs->WinData);  in rr_load_firmware()
1566 	writel(localctrl, &regs->LocalCtrl);  in rr_load_firmware()