161 	reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_enable_interrupts()
187 	reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_disable_interrupts()
192 	reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_disable_interrupts()
326 	reg_data = __raw_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
339 		reg_data = __raw_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
357 	reg_data = __raw_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
384 	reg_data = __raw_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
401 		reg_data = __raw_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
408 	proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET +  in xemaclite_recv_data()
417 			length = ((ntohl(__raw_readl(addr +  in xemaclite_recv_data()
439 	reg_data = __raw_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
471 	reg_data = __raw_readl(addr + XEL_TSR_OFFSET);  in xemaclite_update_address()
475 	while ((__raw_readl(addr + XEL_TSR_OFFSET) &  in xemaclite_update_address()
645 	if ((__raw_readl(base_addr + XEL_RSR_OFFSET) &  in xemaclite_interrupt()
647 	    (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)  in xemaclite_interrupt()
653 	tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
664 	tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_interrupt()
703 	while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &  in xemaclite_mdio_wait()
739 	ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_read()
749 	rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET);  in xemaclite_mdio_read()
786 	ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_write()