129 	void __iomem *base_addr;  member
161 	reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_enable_interrupts()
163 		     drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_enable_interrupts()
166 	__raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_enable_interrupts()
169 	__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_enable_interrupts()
184 	__raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_disable_interrupts()
187 	reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_disable_interrupts()
189 		     drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_disable_interrupts()
192 	reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_disable_interrupts()
194 		     drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_disable_interrupts()
319 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;  in xemaclite_send_data()
381 	addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);  in xemaclite_recv_data()
464 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;  in xemaclite_update_address()
641 	void __iomem *base_addr = lp->base_addr;  in xemaclite_interrupt()  local
645 	if ((__raw_readl(base_addr + XEL_RSR_OFFSET) &  in xemaclite_interrupt()
647 	    (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)  in xemaclite_interrupt()
653 	tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
658 		__raw_writel(tx_status, base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
664 	tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_interrupt()
669 		__raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +  in xemaclite_interrupt()
703 	while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &  in xemaclite_mdio_wait()
739 	ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_read()
742 		     lp->base_addr + XEL_MDIOADDR_OFFSET);  in xemaclite_mdio_read()
744 		     lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_read()
749 	rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET);  in xemaclite_mdio_read()
786 	ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_write()
789 		     lp->base_addr + XEL_MDIOADDR_OFFSET);  in xemaclite_mdio_write()
790 	__raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);  in xemaclite_mdio_write()
792 		     lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_write()
838 		     lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_setup()
1119 	lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);  in xemaclite_of_probe()
1120 	if (IS_ERR(lp->base_addr)) {  in xemaclite_of_probe()
1121 		rc = PTR_ERR(lp->base_addr);  in xemaclite_of_probe()
1142 	__raw_writel(0, lp->base_addr + XEL_TSR_OFFSET);  in xemaclite_of_probe()
1143 	__raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_of_probe()
1170 		 (unsigned int __force)lp->base_addr, ndev->irq);  in xemaclite_of_probe()