Lines Matching refs:ioaddr
276 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
531 void __iomem *ioaddr = rp->base; in rhine_wait_bit() local
535 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); in rhine_wait_bit()
559 void __iomem *ioaddr = rp->base; in rhine_get_events() local
562 intr_status = ioread16(ioaddr + IntrStatus); in rhine_get_events()
565 intr_status |= ioread8(ioaddr + IntrStatus2) << 16; in rhine_get_events()
571 void __iomem *ioaddr = rp->base; in rhine_ack_events() local
574 iowrite8(mask >> 16, ioaddr + IntrStatus2); in rhine_ack_events()
575 iowrite16(mask, ioaddr + IntrStatus); in rhine_ack_events()
586 void __iomem *ioaddr = rp->base; in rhine_power_init() local
591 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); in rhine_power_init()
594 iowrite8(0x80, ioaddr + WOLcgClr); in rhine_power_init()
597 iowrite8(0xFF, ioaddr + WOLcrClr); in rhine_power_init()
600 iowrite8(0x03, ioaddr + WOLcrClr1); in rhine_power_init()
603 wolstat = ioread8(ioaddr + PwrcsrSet); in rhine_power_init()
605 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; in rhine_power_init()
608 iowrite8(0xFF, ioaddr + PwrcsrClr); in rhine_power_init()
610 iowrite8(0x03, ioaddr + PwrcsrClr1); in rhine_power_init()
642 void __iomem *ioaddr = rp->base; in rhine_chip_reset() local
645 iowrite8(Cmd1Reset, ioaddr + ChipCmd1); in rhine_chip_reset()
648 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { in rhine_chip_reset()
653 iowrite8(0x40, ioaddr + MiscCmd); in rhine_chip_reset()
659 cmd1 = ioread8(ioaddr + ChipCmd1); in rhine_chip_reset()
682 void __iomem *ioaddr, in verify_mmio() argument
692 unsigned char b = readb(ioaddr+reg); in verify_mmio()
712 void __iomem *ioaddr = rp->base; in rhine_reload_eeprom() local
732 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); in rhine_reload_eeprom()
751 void __iomem *ioaddr = rp->base; in rhine_kick_tx_threshold() local
754 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig); in rhine_kick_tx_threshold()
788 void __iomem *ioaddr = rp->base; in rhine_update_rx_crc_and_missed_errord() local
791 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs); in rhine_update_rx_crc_and_missed_errord()
792 stats->rx_missed_errors += ioread16(ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
800 iowrite32(0, ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
801 ioread16(ioaddr + RxCRCErrs); in rhine_update_rx_crc_and_missed_errord()
802 ioread16(ioaddr + RxMissed); in rhine_update_rx_crc_and_missed_errord()
829 void __iomem *ioaddr = rp->base; in rhine_napipoll() local
844 if (ioread8(ioaddr + ChipCmd) & CmdTxOn) in rhine_napipoll()
867 iowrite16(enable_mask, ioaddr + IntrEnable); in rhine_napipoll()
908 long pioaddr, void __iomem *ioaddr, int irq) in rhine_init_one_common() argument
933 rp->base = ioaddr; in rhine_init_one_common()
947 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i); in rhine_init_one_common()
959 phy_id = ioread8(ioaddr + 0x6C); in rhine_init_one_common()
1002 name, (long)ioaddr, dev->dev_addr, rp->irq); in rhine_init_one_common()
1045 void __iomem *ioaddr; in rhine_init_one_pci() local
1100 ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size); in rhine_init_one_pci()
1101 if (!ioaddr) { in rhine_init_one_pci()
1111 rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks); in rhine_init_one_pci()
1116 pioaddr, ioaddr, pdev->irq); in rhine_init_one_pci()
1121 pci_iounmap(pdev, ioaddr); in rhine_init_one_pci()
1136 void __iomem *ioaddr; in rhine_init_one_platform() local
1143 ioaddr = devm_ioremap_resource(&pdev->dev, res); in rhine_init_one_platform()
1144 if (IS_ERR(ioaddr)) in rhine_init_one_platform()
1145 return PTR_ERR(ioaddr); in rhine_init_one_platform()
1156 (long)ioaddr, ioaddr, irq); in rhine_init_one_platform()
1330 void __iomem *ioaddr = rp->base; in rhine_check_media() local
1336 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, in rhine_check_media()
1337 ioaddr + ChipCmd1); in rhine_check_media()
1339 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, in rhine_check_media()
1340 ioaddr + ChipCmd1); in rhine_check_media()
1372 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr) in rhine_set_cam() argument
1376 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1382 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_cam()
1385 iowrite8(*addr, ioaddr + MulticastFilter0 + i); in rhine_set_cam()
1389 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam()
1392 iowrite8(0, ioaddr + CamCon); in rhine_set_cam()
1403 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr) in rhine_set_vlan_cam() argument
1405 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam()
1411 iowrite8((u8) idx, ioaddr + CamAddr); in rhine_set_vlan_cam()
1413 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6); in rhine_set_vlan_cam()
1417 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); in rhine_set_vlan_cam()
1420 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam()
1430 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask) in rhine_set_cam_mask() argument
1432 iowrite8(CAMC_CAMEN, ioaddr + CamCon); in rhine_set_cam_mask()
1436 iowrite32(mask, ioaddr + CamMask); in rhine_set_cam_mask()
1439 iowrite8(0, ioaddr + CamCon); in rhine_set_cam_mask()
1449 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask) in rhine_set_vlan_cam_mask() argument
1451 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1455 iowrite32(mask, ioaddr + CamMask); in rhine_set_vlan_cam_mask()
1458 iowrite8(0, ioaddr + CamCon); in rhine_set_vlan_cam_mask()
1471 void __iomem *ioaddr = rp->base; in rhine_init_cam_filter() local
1474 rhine_set_vlan_cam_mask(ioaddr, 0); in rhine_init_cam_filter()
1475 rhine_set_cam_mask(ioaddr, 0); in rhine_init_cam_filter()
1478 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig); in rhine_init_cam_filter()
1479 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_init_cam_filter()
1491 void __iomem *ioaddr = rp->base; in rhine_update_vcam() local
1497 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid); in rhine_update_vcam()
1502 rhine_set_vlan_cam_mask(ioaddr, vCAMmask); in rhine_update_vcam()
1530 void __iomem *ioaddr = rp->base; in init_registers() local
1534 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); in init_registers()
1537 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ in init_registers()
1539 iowrite8(0x20, ioaddr + TxConfig); in init_registers()
1543 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); in init_registers()
1544 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); in init_registers()
1553 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable); in init_registers()
1556 ioaddr + ChipCmd); in init_registers()
1563 void __iomem *ioaddr = rp->base; in rhine_enable_linkmon() local
1565 iowrite8(0, ioaddr + MIICmd); in rhine_enable_linkmon()
1566 iowrite8(MII_BMSR, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1567 iowrite8(0x80, ioaddr + MIICmd); in rhine_enable_linkmon()
1571 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); in rhine_enable_linkmon()
1577 void __iomem *ioaddr = rp->base; in rhine_disable_linkmon() local
1579 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1582 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR in rhine_disable_linkmon()
1588 iowrite8(0x80, ioaddr + MIICmd); in rhine_disable_linkmon()
1593 iowrite8(0, ioaddr + MIICmd); in rhine_disable_linkmon()
1604 void __iomem *ioaddr = rp->base; in mdio_read() local
1610 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_read()
1611 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_read()
1612 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ in mdio_read()
1614 result = ioread16(ioaddr + MIIData); in mdio_read()
1623 void __iomem *ioaddr = rp->base; in mdio_write() local
1628 iowrite8(phy_id, ioaddr + MIIPhyAddr); in mdio_write()
1629 iowrite8(regnum, ioaddr + MIIRegAddr); in mdio_write()
1630 iowrite16(value, ioaddr + MIIData); in mdio_write()
1631 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ in mdio_write()
1657 void __iomem *ioaddr = rp->base; in rhine_open() local
1678 __func__, ioread16(ioaddr + ChipCmd), in rhine_open()
1724 void __iomem *ioaddr = rp->base; in rhine_tx_timeout() local
1727 ioread16(ioaddr + IntrStatus), in rhine_tx_timeout()
1738 void __iomem *ioaddr = rp->base; in rhine_start_tx() local
1813 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); in rhine_start_tx()
1816 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_start_tx()
1817 ioaddr + ChipCmd1); in rhine_start_tx()
2087 void __iomem *ioaddr = rp->base; in rhine_restart_tx() local
2101 ioaddr + TxRingPtr); in rhine_restart_tx()
2103 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, in rhine_restart_tx()
2104 ioaddr + ChipCmd); in rhine_restart_tx()
2108 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); in rhine_restart_tx()
2110 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, in rhine_restart_tx()
2111 ioaddr + ChipCmd1); in rhine_restart_tx()
2179 void __iomem *ioaddr = rp->base; in rhine_set_rx_mode() local
2186 iowrite32(0xffffffff, ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2187 iowrite32(0xffffffff, ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2191 iowrite32(0xffffffff, ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2192 iowrite32(0xffffffff, ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2199 rhine_set_cam(ioaddr, i, ha->addr); in rhine_set_rx_mode()
2203 rhine_set_cam_mask(ioaddr, mCAMmask); in rhine_set_rx_mode()
2211 iowrite32(mc_filter[0], ioaddr + MulticastFilter0); in rhine_set_rx_mode()
2212 iowrite32(mc_filter[1], ioaddr + MulticastFilter1); in rhine_set_rx_mode()
2217 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_set_rx_mode()
2219 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1); in rhine_set_rx_mode()
2221 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig); in rhine_set_rx_mode()
2350 void __iomem *ioaddr = rp->base; in rhine_close() local
2357 ioread16(ioaddr + ChipCmd)); in rhine_close()
2360 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); in rhine_close()
2365 iowrite16(CmdStop, ioaddr + ChipCmd); in rhine_close()
2408 void __iomem *ioaddr = rp->base; in rhine_shutdown_pci() local
2417 iowrite8(0x04, ioaddr + WOLcgClr); in rhine_shutdown_pci()
2422 iowrite8(WOLmagic, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2427 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); in rhine_shutdown_pci()
2431 iowrite8(WOLbmcast, ioaddr + WOLcgSet); in rhine_shutdown_pci()
2434 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2437 iowrite8(WOLucast, ioaddr + WOLcrSet); in rhine_shutdown_pci()
2441 iowrite8(0x01, ioaddr + PwcfgSet); in rhine_shutdown_pci()
2442 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); in rhine_shutdown_pci()
2448 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); in rhine_shutdown_pci()