964 	u32 phy   = priv->phy[priv->phy_num];  in tlan_ioctl()  local
971 		data->phy_id = phy;  in tlan_ioctl()
1706 	u32		phy;  in tlan_handle_status_check()  local
1724 		phy = priv->phy[priv->phy_num];  in tlan_handle_status_check()
1733 			tlan_mii_read_reg(dev, phy, TLAN_TLPHY_STS, &tlphy_sts);  in tlan_handle_status_check()
1734 			tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl);  in tlan_handle_status_check()
1738 				tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL,  in tlan_handle_status_check()
1743 				tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL,  in tlan_handle_status_check()
2263 	u32		phy;  in tlan_finish_reset()  local
2272 	phy = priv->phy[priv->phy_num];  in tlan_finish_reset()
2283 	tlan_mii_read_reg(dev, phy, MII_GEN_ID_HI, &tlphy_id1);  in tlan_finish_reset()
2284 	tlan_mii_read_reg(dev, phy, MII_GEN_ID_LO, &tlphy_id2);  in tlan_finish_reset()
2291 		tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_finish_reset()
2293 		tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_finish_reset()
2298 				tlan_mii_read_reg(dev, phy, MII_AN_LPA,  in tlan_finish_reset()
2300 				tlan_mii_read_reg(dev, phy, TLAN_TLPHY_PAR,  in tlan_finish_reset()
2331 		tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl);  in tlan_finish_reset()
2333 		tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);  in tlan_finish_reset()
2430 	u16 i, data0, data1, data2, data3, phy;  in tlan_phy_print()  local
2432 	phy = priv->phy[priv->phy_num];  in tlan_phy_print()
2436 	} else if (phy <= TLAN_PHY_MAX_ADDR) {  in tlan_phy_print()
2437 		netdev_info(dev, "PHY 0x%02x\n", phy);  in tlan_phy_print()
2440 			tlan_mii_read_reg(dev, phy, i, &data0);  in tlan_phy_print()
2441 			tlan_mii_read_reg(dev, phy, i + 1, &data1);  in tlan_phy_print()
2442 			tlan_mii_read_reg(dev, phy, i + 2, &data2);  in tlan_phy_print()
2443 			tlan_mii_read_reg(dev, phy, i + 3, &data3);  in tlan_phy_print()
2479 	u32		phy;  in tlan_phy_detect()  local
2489 		priv->phy[0] = TLAN_PHY_MAX_ADDR;  in tlan_phy_detect()
2491 		priv->phy[0] = TLAN_PHY_NONE;  in tlan_phy_detect()
2493 	priv->phy[1] = TLAN_PHY_NONE;  in tlan_phy_detect()
2494 	for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {  in tlan_phy_detect()
2495 		tlan_mii_read_reg(dev, phy, MII_GEN_CTL, &control);  in tlan_phy_detect()
2496 		tlan_mii_read_reg(dev, phy, MII_GEN_ID_HI, &hi);  in tlan_phy_detect()
2497 		tlan_mii_read_reg(dev, phy, MII_GEN_ID_LO, &lo);  in tlan_phy_detect()
2502 				 phy, control, hi, lo);  in tlan_phy_detect()
2503 			if ((priv->phy[1] == TLAN_PHY_NONE) &&  in tlan_phy_detect()
2504 			    (phy != TLAN_PHY_MAX_ADDR)) {  in tlan_phy_detect()
2505 				priv->phy[1] = phy;  in tlan_phy_detect()
2510 	if (priv->phy[1] != TLAN_PHY_NONE)  in tlan_phy_detect()
2512 	else if (priv->phy[0] != TLAN_PHY_NONE)  in tlan_phy_detect()
2530 	tlan_mii_write_reg(dev, priv->phy[priv->phy_num], MII_GEN_CTL, value);  in tlan_phy_power_down()
2531 	if ((priv->phy_num == 0) && (priv->phy[1] != TLAN_PHY_NONE)) {  in tlan_phy_power_down()
2536 		tlan_mii_write_reg(dev, priv->phy[1], MII_GEN_CTL, value);  in tlan_phy_power_down()
2558 	tlan_mii_write_reg(dev, priv->phy[priv->phy_num], MII_GEN_CTL, value);  in tlan_phy_power_up()
2574 	u16		phy;  in tlan_phy_reset()  local
2578 	phy = priv->phy[priv->phy_num];  in tlan_phy_reset()
2583 	tlan_mii_write_reg(dev, phy, MII_GEN_CTL, value);  in tlan_phy_reset()
2585 		tlan_mii_read_reg(dev, phy, MII_GEN_CTL, &value);  in tlan_phy_reset()
2609 	u16		phy;  in tlan_phy_start_link()  local
2613 	phy = priv->phy[priv->phy_num];  in tlan_phy_start_link()
2615 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_start_link()
2616 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &ability);  in tlan_phy_start_link()
2623 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x0000);  in tlan_phy_start_link()
2627 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x0100);  in tlan_phy_start_link()
2630 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x2000);  in tlan_phy_start_link()
2634 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x2100);  in tlan_phy_start_link()
2638 			tlan_mii_write_reg(dev, phy, MII_AN_ADV,  in tlan_phy_start_link()
2641 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x1000);  in tlan_phy_start_link()
2643 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL, 0x1200);  in tlan_phy_start_link()
2665 		tlan_mii_read_reg(dev, phy, TLAN_TLPHY_CTL, &tctl);  in tlan_phy_start_link()
2677 		tlan_mii_write_reg(dev, phy, MII_GEN_CTL, control);  in tlan_phy_start_link()
2678 		tlan_mii_write_reg(dev, phy, TLAN_TLPHY_CTL, tctl);  in tlan_phy_start_link()
2697 	u16		phy;  in tlan_phy_finish_auto_neg()  local
2700 	phy = priv->phy[priv->phy_num];  in tlan_phy_finish_auto_neg()
2702 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_finish_auto_neg()
2704 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &status);  in tlan_phy_finish_auto_neg()
2715 	tlan_mii_read_reg(dev, phy, MII_AN_ADV, &an_adv);  in tlan_phy_finish_auto_neg()
2716 	tlan_mii_read_reg(dev, phy, MII_AN_LPA, &an_lpa);  in tlan_phy_finish_auto_neg()
2735 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL,  in tlan_phy_finish_auto_neg()
2739 			tlan_mii_write_reg(dev, phy, MII_GEN_CTL,  in tlan_phy_finish_auto_neg()
2773 	u16     phy;  in tlan_phy_monitor()  local
2776 	phy = priv->phy[priv->phy_num];  in tlan_phy_monitor()
2779 	tlan_mii_read_reg(dev, phy, MII_GEN_STS, &phy_status);  in tlan_phy_monitor()
2794 				tlan_mii_write_reg(dev, priv->phy[0],  in tlan_phy_monitor()
2855 tlan_mii_read_reg(struct net_device *dev, u16 phy, u16 reg, u16 *val)  in tlan_mii_read_reg()  argument
2880 	tlan_mii_send_data(dev->base_addr, phy, 5);	/* device #      */  in tlan_mii_read_reg()
3027 tlan_mii_write_reg(struct net_device *dev, u16 phy, u16 reg, u16 val)  in tlan_mii_write_reg()  argument
3048 	tlan_mii_send_data(dev->base_addr, phy, 5);	/* device #      */  in tlan_mii_write_reg()