657 	void __iomem			*switch_regs;  member
1589 		val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));  in gbe_update_stats_ver14()
1597 		writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));  in gbe_update_stats_ver14()
2223 	reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));  in gbe_open()
2247 	writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));  in gbe_open()
2250 	writel(GBE_CTL_P0_ENABLE, GBE_REG_ADDR(gbe_dev, switch_regs, control));  in gbe_open()
2253 	writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,  in gbe_open()
2342 	slave->port_regs = gbe_dev->switch_regs + port_reg_ofs +  in init_slave()
2344 	slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs +  in init_slave()
2540 	gbe_dev->switch_regs = regs;  in set_xgbe_ethss10_priv()
2572 		gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +  in set_xgbe_ethss10_priv()
2575 	gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET;  in set_xgbe_ethss10_priv()
2588 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_xgbe_ethss10_priv()
2589 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_xgbe_ethss10_priv()
2590 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_xgbe_ethss10_priv()
2591 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_xgbe_ethss10_priv()
2592 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);  in set_xgbe_ethss10_priv()
2663 	gbe_dev->switch_regs = regs;  in set_gbe_ethss14_priv()
2675 	gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET;  in set_gbe_ethss14_priv()
2679 			gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET +  in set_gbe_ethss14_priv()
2683 	gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET;  in set_gbe_ethss14_priv()
2695 	GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_gbe_ethss14_priv()
2696 	GBE_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_gbe_ethss14_priv()
2697 	GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset);  in set_gbe_ethss14_priv()
2698 	GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_gbe_ethss14_priv()
2699 	GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_gbe_ethss14_priv()
2700 	GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);  in set_gbe_ethss14_priv()
2738 	gbe_dev->switch_regs = regs;  in set_gbenu_ethss_priv()
2741 	gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET;  in set_gbenu_ethss_priv()
2744 		gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +  in set_gbenu_ethss_priv()
2747 	gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET;  in set_gbenu_ethss_priv()
2765 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_gbenu_ethss_priv()
2766 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_gbenu_ethss_priv()
2767 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_gbenu_ethss_priv()
2768 	GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_gbenu_ethss_priv()