154 #define cpmac_write(base, reg, val)	(writel(val, (void __iomem *)(base) + \  macro
282 	cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |  in cpmac_mdio_read()
295 	cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |  in cpmac_mdio_write()
311 	cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |  in cpmac_mdio_reset()
330 		cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |  in cpmac_set_multicast_list()
333 		cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);  in cpmac_set_multicast_list()
336 			cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);  in cpmac_set_multicast_list()
337 			cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);  in cpmac_set_multicast_list()
360 			cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);  in cpmac_set_multicast_list()
361 			cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);  in cpmac_set_multicast_list()
373 	cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);  in cpmac_rx_one()
502 		cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);  in cpmac_poll()
515 		cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);  in cpmac_poll()
587 	cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);  in cpmac_start_xmit()
598 	cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);  in cpmac_end_xmit()
630 	cpmac_write(priv->regs, CPMAC_RX_CONTROL,  in cpmac_hw_stop()
632 	cpmac_write(priv->regs, CPMAC_TX_CONTROL,  in cpmac_hw_stop()
635 		cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);  in cpmac_hw_stop()
636 		cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);  in cpmac_hw_stop()
638 	cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);  in cpmac_hw_stop()
639 	cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);  in cpmac_hw_stop()
640 	cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);  in cpmac_hw_stop()
641 	cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);  in cpmac_hw_stop()
642 	cpmac_write(priv->regs, CPMAC_MAC_CONTROL,  in cpmac_hw_stop()
654 		cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);  in cpmac_hw_start()
655 		cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);  in cpmac_hw_start()
657 	cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);  in cpmac_hw_start()
659 	cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |  in cpmac_hw_start()
661 	cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);  in cpmac_hw_start()
663 		cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);  in cpmac_hw_start()
664 	cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);  in cpmac_hw_start()
665 	cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |  in cpmac_hw_start()
668 	cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);  in cpmac_hw_start()
669 	cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);  in cpmac_hw_start()
670 	cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);  in cpmac_hw_start()
671 	cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);  in cpmac_hw_start()
672 	cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);  in cpmac_hw_start()
673 	cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);  in cpmac_hw_start()
674 	cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);  in cpmac_hw_start()
675 	cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);  in cpmac_hw_start()
676 	cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);  in cpmac_hw_start()
678 	cpmac_write(priv->regs, CPMAC_RX_CONTROL,  in cpmac_hw_start()
680 	cpmac_write(priv->regs, CPMAC_TX_CONTROL,  in cpmac_hw_start()
682 	cpmac_write(priv->regs, CPMAC_MAC_CONTROL,  in cpmac_hw_start()
741 	cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);  in cpmac_hw_error()
776 	cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);  in cpmac_check_status()
799 			cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);  in cpmac_irq()
804 	cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);  in cpmac_irq()
1062 		cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);  in cpmac_stop()
1063 	cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);  in cpmac_stop()
1064 	cpmac_write(priv->regs, CPMAC_MBP, 0);  in cpmac_stop()