Lines Matching refs:gp
118 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg) in __sungem_phy_read() argument
128 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_read()
131 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_read()
146 struct gem *gp = netdev_priv(dev); in _sungem_phy_read() local
147 return __sungem_phy_read(gp, mii_id, reg); in _sungem_phy_read()
150 static inline u16 sungem_phy_read(struct gem *gp, int reg) in sungem_phy_read() argument
152 return __sungem_phy_read(gp, gp->mii_phy_addr, reg); in sungem_phy_read()
155 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val) in __sungem_phy_write() argument
166 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_write()
169 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_write()
179 struct gem *gp = netdev_priv(dev); in _sungem_phy_write() local
180 __sungem_phy_write(gp, mii_id, reg, val & 0xffff); in _sungem_phy_write()
183 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val) in sungem_phy_write() argument
185 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val); in sungem_phy_write()
188 static inline void gem_enable_ints(struct gem *gp) in gem_enable_ints() argument
191 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints()
194 static inline void gem_disable_ints(struct gem *gp) in gem_disable_ints() argument
197 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints()
198 (void)readl(gp->regs + GREG_IMASK); /* write posting */ in gem_disable_ints()
201 static void gem_get_cell(struct gem *gp) in gem_get_cell() argument
203 BUG_ON(gp->cell_enabled < 0); in gem_get_cell()
204 gp->cell_enabled++; in gem_get_cell()
206 if (gp->cell_enabled == 1) { in gem_get_cell()
208 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); in gem_get_cell()
215 static void gem_put_cell(struct gem *gp) in gem_put_cell() argument
217 BUG_ON(gp->cell_enabled <= 0); in gem_put_cell()
218 gp->cell_enabled--; in gem_put_cell()
220 if (gp->cell_enabled == 0) { in gem_put_cell()
222 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); in gem_put_cell()
228 static inline void gem_netif_stop(struct gem *gp) in gem_netif_stop() argument
230 gp->dev->trans_start = jiffies; /* prevent tx timeout */ in gem_netif_stop()
231 napi_disable(&gp->napi); in gem_netif_stop()
232 netif_tx_disable(gp->dev); in gem_netif_stop()
235 static inline void gem_netif_start(struct gem *gp) in gem_netif_start() argument
241 netif_wake_queue(gp->dev); in gem_netif_start()
242 napi_enable(&gp->napi); in gem_netif_start()
245 static void gem_schedule_reset(struct gem *gp) in gem_schedule_reset() argument
247 gp->reset_task_pending = 1; in gem_schedule_reset()
248 schedule_work(&gp->reset_task); in gem_schedule_reset()
251 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) in gem_handle_mif_event() argument
253 if (netif_msg_intr(gp)) in gem_handle_mif_event()
254 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); in gem_handle_mif_event()
257 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pcs_interrupt() argument
259 u32 pcs_istat = readl(gp->regs + PCS_ISTAT); in gem_pcs_interrupt()
262 if (netif_msg_intr(gp)) in gem_pcs_interrupt()
264 gp->dev->name, pcs_istat); in gem_pcs_interrupt()
275 pcs_miistat = readl(gp->regs + PCS_MIISTAT); in gem_pcs_interrupt()
278 (readl(gp->regs + PCS_MIISTAT) & in gem_pcs_interrupt()
293 netif_carrier_on(gp->dev); in gem_pcs_interrupt()
296 netif_carrier_off(gp->dev); in gem_pcs_interrupt()
300 if (!timer_pending(&gp->link_timer)) in gem_pcs_interrupt()
307 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_txmac_interrupt() argument
309 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); in gem_txmac_interrupt()
311 if (netif_msg_intr(gp)) in gem_txmac_interrupt()
313 gp->dev->name, txmac_stat); in gem_txmac_interrupt()
360 static int gem_rxmac_reset(struct gem *gp) in gem_rxmac_reset() argument
362 struct net_device *dev = gp->dev; in gem_rxmac_reset()
368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset()
370 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) in gem_rxmac_reset()
379 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset()
380 gp->regs + MAC_RXCFG); in gem_rxmac_reset()
382 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) in gem_rxmac_reset()
392 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
394 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) in gem_rxmac_reset()
406 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset()
407 gp->regs + GREG_SWRST); in gem_rxmac_reset()
409 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) in gem_rxmac_reset()
420 struct gem_rxd *rxd = &gp->init_block->rxd[i]; in gem_rxmac_reset()
422 if (gp->rx_skbs[i] == NULL) { in gem_rxmac_reset()
427 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_rxmac_reset()
429 gp->rx_new = gp->rx_old = 0; in gem_rxmac_reset()
432 desc_dma = (u64) gp->gblock_dvma; in gem_rxmac_reset()
434 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset()
435 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset()
436 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_rxmac_reset()
439 writel(val, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
440 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_rxmac_reset()
443 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
447 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
448 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_rxmac_reset()
449 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_rxmac_reset()
450 writel(val, gp->regs + RXDMA_PTHRESH); in gem_rxmac_reset()
451 val = readl(gp->regs + RXDMA_CFG); in gem_rxmac_reset()
452 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
453 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_rxmac_reset()
454 val = readl(gp->regs + MAC_RXCFG); in gem_rxmac_reset()
455 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_rxmac_reset()
460 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_rxmac_interrupt() argument
462 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); in gem_rxmac_interrupt()
465 if (netif_msg_intr(gp)) in gem_rxmac_interrupt()
467 gp->dev->name, rxmac_stat); in gem_rxmac_interrupt()
470 u32 smac = readl(gp->regs + MAC_SMACHINE); in gem_rxmac_interrupt()
476 ret = gem_rxmac_reset(gp); in gem_rxmac_interrupt()
494 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mac_interrupt() argument
496 u32 mac_cstat = readl(gp->regs + MAC_CSTAT); in gem_mac_interrupt()
498 if (netif_msg_intr(gp)) in gem_mac_interrupt()
500 gp->dev->name, mac_cstat); in gem_mac_interrupt()
507 gp->pause_entered++; in gem_mac_interrupt()
510 gp->pause_last_time_recvd = (mac_cstat >> 16); in gem_mac_interrupt()
515 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mif_interrupt() argument
517 u32 mif_status = readl(gp->regs + MIF_STATUS); in gem_mif_interrupt()
523 gem_handle_mif_event(gp, reg_val, changed_bits); in gem_mif_interrupt()
528 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pci_interrupt() argument
530 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); in gem_pci_interrupt()
532 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_pci_interrupt()
533 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_pci_interrupt()
554 pci_read_config_word(gp->pdev, PCI_STATUS, in gem_pci_interrupt()
578 pci_write_config_word(gp->pdev, in gem_pci_interrupt()
591 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_abnormal_irq() argument
595 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
597 gp->dev->name); in gem_abnormal_irq()
603 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
605 gp->dev->name); in gem_abnormal_irq()
612 if (gem_pcs_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
617 if (gem_txmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
622 if (gem_rxmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
627 if (gem_mac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
632 if (gem_mif_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
637 if (gem_pci_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
644 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_tx() argument
648 entry = gp->tx_old; in gem_tx()
657 if (netif_msg_tx_done(gp)) in gem_tx()
659 gp->dev->name, entry); in gem_tx()
660 skb = gp->tx_skbs[entry]; in gem_tx()
677 gp->tx_skbs[entry] = NULL; in gem_tx()
681 txd = &gp->init_block->txd[entry]; in gem_tx()
686 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); in gem_tx()
693 gp->tx_old = entry; in gem_tx()
703 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) { in gem_tx()
708 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_tx()
714 static __inline__ void gem_post_rxds(struct gem *gp, int limit) in gem_post_rxds() argument
718 cluster_start = curr = (gp->rx_new & ~(4 - 1)); in gem_post_rxds()
726 &gp->init_block->rxd[cluster_start]; in gem_post_rxds()
728 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_post_rxds()
740 writel(kick, gp->regs + RXDMA_KICK); in gem_post_rxds()
758 static int gem_rx(struct gem *gp, int work_to_do) in gem_rx() argument
760 struct net_device *dev = gp->dev; in gem_rx()
765 if (netif_msg_rx_status(gp)) in gem_rx()
767 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); in gem_rx()
769 entry = gp->rx_new; in gem_rx()
771 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
773 struct gem_rxd *rxd = &gp->init_block->rxd[entry]; in gem_rx()
793 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
801 skb = gp->rx_skbs[entry]; in gem_rx()
821 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); in gem_rx()
826 pci_unmap_page(gp->pdev, dma_addr, in gem_rx()
827 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
829 gp->rx_skbs[entry] = new_skb; in gem_rx()
830 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_rx()
831 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, in gem_rx()
834 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
850 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
852 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
861 skb->protocol = eth_type_trans(skb, gp->dev); in gem_rx()
863 napi_gro_receive(&gp->napi, skb); in gem_rx()
872 gem_post_rxds(gp, entry); in gem_rx()
874 gp->rx_new = entry; in gem_rx()
877 netdev_info(gp->dev, "Memory squeeze, deferring packet\n"); in gem_rx()
884 struct gem *gp = container_of(napi, struct gem, napi); in gem_poll() local
885 struct net_device *dev = gp->dev; in gem_poll()
891 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) { in gem_poll()
901 reset = gem_abnormal_irq(dev, gp, gp->status); in gem_poll()
904 gem_schedule_reset(gp); in gem_poll()
911 gem_tx(dev, gp, gp->status); in gem_poll()
918 work_done += gem_rx(gp, budget - work_done); in gem_poll()
923 gp->status = readl(gp->regs + GREG_STAT); in gem_poll()
924 } while (gp->status & GREG_STAT_NAPI); in gem_poll()
927 gem_enable_ints(gp); in gem_poll()
935 struct gem *gp = netdev_priv(dev); in gem_interrupt() local
937 if (napi_schedule_prep(&gp->napi)) { in gem_interrupt()
938 u32 gem_status = readl(gp->regs + GREG_STAT); in gem_interrupt()
941 napi_enable(&gp->napi); in gem_interrupt()
944 if (netif_msg_intr(gp)) in gem_interrupt()
946 gp->dev->name, gem_status); in gem_interrupt()
948 gp->status = gem_status; in gem_interrupt()
949 gem_disable_ints(gp); in gem_interrupt()
950 __napi_schedule(&gp->napi); in gem_interrupt()
963 struct gem *gp = netdev_priv(dev); in gem_poll_controller() local
965 disable_irq(gp->pdev->irq); in gem_poll_controller()
966 gem_interrupt(gp->pdev->irq, dev); in gem_poll_controller()
967 enable_irq(gp->pdev->irq); in gem_poll_controller()
973 struct gem *gp = netdev_priv(dev); in gem_tx_timeout() local
978 readl(gp->regs + TXDMA_CFG), in gem_tx_timeout()
979 readl(gp->regs + MAC_TXSTAT), in gem_tx_timeout()
980 readl(gp->regs + MAC_TXCFG)); in gem_tx_timeout()
982 readl(gp->regs + RXDMA_CFG), in gem_tx_timeout()
983 readl(gp->regs + MAC_RXSTAT), in gem_tx_timeout()
984 readl(gp->regs + MAC_RXCFG)); in gem_tx_timeout()
986 gem_schedule_reset(gp); in gem_tx_timeout()
1001 struct gem *gp = netdev_priv(dev); in gem_start_xmit() local
1015 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) { in gem_start_xmit()
1024 entry = gp->tx_new; in gem_start_xmit()
1025 gp->tx_skbs[entry] = skb; in gem_start_xmit()
1028 struct gem_txd *txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1033 mapping = pci_map_page(gp->pdev, in gem_start_xmit()
1059 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), in gem_start_xmit()
1071 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag, in gem_start_xmit()
1077 txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1087 txd = &gp->init_block->txd[first_entry]; in gem_start_xmit()
1094 gp->tx_new = entry; in gem_start_xmit()
1095 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) { in gem_start_xmit()
1104 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_start_xmit()
1107 if (netif_msg_tx_queued(gp)) in gem_start_xmit()
1111 writel(gp->tx_new, gp->regs + TXDMA_KICK); in gem_start_xmit()
1116 static void gem_pcs_reset(struct gem *gp) in gem_pcs_reset() argument
1122 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1124 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1127 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { in gem_pcs_reset()
1133 netdev_warn(gp->dev, "PCS reset bit would not clear\n"); in gem_pcs_reset()
1136 static void gem_pcs_reinit_adv(struct gem *gp) in gem_pcs_reinit_adv() argument
1143 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1145 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1150 val = readl(gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1153 writel(val, gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1158 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1161 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1163 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1165 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1171 val = readl(gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1172 if (gp->phy_type == phy_serialink) in gem_pcs_reinit_adv()
1176 writel(val, gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1181 static void gem_reset(struct gem *gp) in gem_reset() argument
1187 writel(0xffffffff, gp->regs + GREG_IMASK); in gem_reset()
1190 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, in gem_reset()
1191 gp->regs + GREG_SWRST); in gem_reset()
1197 val = readl(gp->regs + GREG_SWRST); in gem_reset()
1203 netdev_err(gp->dev, "SW reset is ghetto\n"); in gem_reset()
1205 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) in gem_reset()
1206 gem_pcs_reinit_adv(gp); in gem_reset()
1209 static void gem_start_dma(struct gem *gp) in gem_start_dma() argument
1214 val = readl(gp->regs + TXDMA_CFG); in gem_start_dma()
1215 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_start_dma()
1216 val = readl(gp->regs + RXDMA_CFG); in gem_start_dma()
1217 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_start_dma()
1218 val = readl(gp->regs + MAC_TXCFG); in gem_start_dma()
1219 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_start_dma()
1220 val = readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1221 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_start_dma()
1223 (void) readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1226 gem_enable_ints(gp); in gem_start_dma()
1228 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_start_dma()
1233 static void gem_stop_dma(struct gem *gp) in gem_stop_dma() argument
1238 val = readl(gp->regs + TXDMA_CFG); in gem_stop_dma()
1239 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_stop_dma()
1240 val = readl(gp->regs + RXDMA_CFG); in gem_stop_dma()
1241 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_stop_dma()
1242 val = readl(gp->regs + MAC_TXCFG); in gem_stop_dma()
1243 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_stop_dma()
1244 val = readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1245 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_stop_dma()
1247 (void) readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1254 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep) in gem_begin_auto_negotiation() argument
1261 if (gp->phy_type != phy_mii_mdio0 && in gem_begin_auto_negotiation()
1262 gp->phy_type != phy_mii_mdio1) in gem_begin_auto_negotiation()
1266 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1267 features = gp->phy_mii.def->features; in gem_begin_auto_negotiation()
1272 if (gp->phy_mii.advertising != 0) in gem_begin_auto_negotiation()
1273 advertise &= gp->phy_mii.advertising; in gem_begin_auto_negotiation()
1275 autoneg = gp->want_autoneg; in gem_begin_auto_negotiation()
1276 speed = gp->phy_mii.speed; in gem_begin_auto_negotiation()
1277 duplex = gp->phy_mii.duplex; in gem_begin_auto_negotiation()
1312 if (!netif_device_present(gp->dev)) { in gem_begin_auto_negotiation()
1313 gp->phy_mii.autoneg = gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1314 gp->phy_mii.speed = speed; in gem_begin_auto_negotiation()
1315 gp->phy_mii.duplex = duplex; in gem_begin_auto_negotiation()
1320 gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1322 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1323 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); in gem_begin_auto_negotiation()
1324 gp->lstate = link_aneg; in gem_begin_auto_negotiation()
1326 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1327 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); in gem_begin_auto_negotiation()
1328 gp->lstate = link_force_ok; in gem_begin_auto_negotiation()
1332 gp->timer_ticks = 0; in gem_begin_auto_negotiation()
1333 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_begin_auto_negotiation()
1339 static int gem_set_link_modes(struct gem *gp) in gem_set_link_modes() argument
1341 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0); in gem_set_link_modes()
1349 if (found_mii_phy(gp)) { in gem_set_link_modes()
1350 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) in gem_set_link_modes()
1352 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); in gem_set_link_modes()
1353 speed = gp->phy_mii.speed; in gem_set_link_modes()
1354 pause = gp->phy_mii.pause; in gem_set_link_modes()
1355 } else if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1356 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1357 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1359 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) in gem_set_link_modes()
1364 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n", in gem_set_link_modes()
1379 writel(val, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1383 (gp->phy_type == phy_mii_mdio0 || in gem_set_link_modes()
1384 gp->phy_type == phy_mii_mdio1)) { in gem_set_link_modes()
1393 writel(val, gp->regs + MAC_XIFCFG); in gem_set_link_modes()
1399 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1400 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1402 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1403 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1405 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1406 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1408 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1409 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1412 if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1413 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1414 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1421 writel(512, gp->regs + MAC_STIME); in gem_set_link_modes()
1423 writel(64, gp->regs + MAC_STIME); in gem_set_link_modes()
1424 val = readl(gp->regs + MAC_MCCFG); in gem_set_link_modes()
1429 writel(val, gp->regs + MAC_MCCFG); in gem_set_link_modes()
1431 gem_start_dma(gp); in gem_set_link_modes()
1435 if (netif_msg_link(gp)) { in gem_set_link_modes()
1437 netdev_info(gp->dev, in gem_set_link_modes()
1439 gp->rx_fifo_sz, in gem_set_link_modes()
1440 gp->rx_pause_off, in gem_set_link_modes()
1441 gp->rx_pause_on); in gem_set_link_modes()
1443 netdev_info(gp->dev, "Pause is disabled\n"); in gem_set_link_modes()
1450 static int gem_mdio_link_not_up(struct gem *gp) in gem_mdio_link_not_up() argument
1452 switch (gp->lstate) { in gem_mdio_link_not_up()
1454 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1456 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, in gem_mdio_link_not_up()
1457 gp->last_forced_speed, DUPLEX_HALF); in gem_mdio_link_not_up()
1458 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1459 gp->lstate = link_force_ok; in gem_mdio_link_not_up()
1466 if (gp->phy_mii.def->magic_aneg) in gem_mdio_link_not_up()
1468 netif_info(gp, link, gp->dev, "switching to forced 100bt\n"); in gem_mdio_link_not_up()
1470 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, in gem_mdio_link_not_up()
1472 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1473 gp->lstate = link_force_try; in gem_mdio_link_not_up()
1480 if (gp->phy_mii.speed == SPEED_100) { in gem_mdio_link_not_up()
1481 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, in gem_mdio_link_not_up()
1483 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1484 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1496 struct gem *gp = (struct gem *) data; in gem_link_timer() local
1497 struct net_device *dev = gp->dev; in gem_link_timer()
1501 if (gp->reset_task_pending) in gem_link_timer()
1504 if (gp->phy_type == phy_serialink || in gem_link_timer()
1505 gp->phy_type == phy_serdes) { in gem_link_timer()
1506 u32 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1509 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1512 if (gp->lstate == link_up) in gem_link_timer()
1515 gp->lstate = link_up; in gem_link_timer()
1517 (void)gem_set_link_modes(gp); in gem_link_timer()
1521 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { in gem_link_timer()
1527 if (gp->lstate == link_force_try && gp->want_autoneg) { in gem_link_timer()
1528 gp->lstate = link_force_ret; in gem_link_timer()
1529 gp->last_forced_speed = gp->phy_mii.speed; in gem_link_timer()
1530 gp->timer_ticks = 5; in gem_link_timer()
1531 if (netif_msg_link(gp)) in gem_link_timer()
1534 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); in gem_link_timer()
1535 } else if (gp->lstate != link_up) { in gem_link_timer()
1536 gp->lstate = link_up; in gem_link_timer()
1538 if (gem_set_link_modes(gp)) in gem_link_timer()
1545 if (gp->lstate == link_up) { in gem_link_timer()
1546 gp->lstate = link_down; in gem_link_timer()
1547 netif_info(gp, link, dev, "Link down\n"); in gem_link_timer()
1549 gem_schedule_reset(gp); in gem_link_timer()
1552 } else if (++gp->timer_ticks > 10) { in gem_link_timer()
1553 if (found_mii_phy(gp)) in gem_link_timer()
1554 restart_aneg = gem_mdio_link_not_up(gp); in gem_link_timer()
1560 gem_begin_auto_negotiation(gp, NULL); in gem_link_timer()
1564 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_link_timer()
1567 static void gem_clean_rings(struct gem *gp) in gem_clean_rings() argument
1569 struct gem_init_block *gb = gp->init_block; in gem_clean_rings()
1578 if (gp->rx_skbs[i] != NULL) { in gem_clean_rings()
1579 skb = gp->rx_skbs[i]; in gem_clean_rings()
1581 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1582 RX_BUF_ALLOC_SIZE(gp), in gem_clean_rings()
1585 gp->rx_skbs[i] = NULL; in gem_clean_rings()
1593 if (gp->tx_skbs[i] != NULL) { in gem_clean_rings()
1597 skb = gp->tx_skbs[i]; in gem_clean_rings()
1598 gp->tx_skbs[i] = NULL; in gem_clean_rings()
1605 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1617 static void gem_init_rings(struct gem *gp) in gem_init_rings() argument
1619 struct gem_init_block *gb = gp->init_block; in gem_init_rings()
1620 struct net_device *dev = gp->dev; in gem_init_rings()
1624 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; in gem_init_rings()
1626 gem_clean_rings(gp); in gem_init_rings()
1628 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, in gem_init_rings()
1635 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL); in gem_init_rings()
1642 gp->rx_skbs[i] = skb; in gem_init_rings()
1643 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_init_rings()
1644 dma_addr = pci_map_page(gp->pdev, in gem_init_rings()
1647 RX_BUF_ALLOC_SIZE(gp), in gem_init_rings()
1651 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_init_rings()
1666 static void gem_init_phy(struct gem *gp) in gem_init_phy() argument
1671 mifcfg = readl(gp->regs + MIF_CFG); in gem_init_phy()
1673 writel(mifcfg, gp->regs + MIF_CFG); in gem_init_phy()
1675 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { in gem_init_phy()
1684 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); in gem_init_phy()
1690 sungem_phy_write(gp, MII_BMCR, BMCR_RESET); in gem_init_phy()
1692 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) in gem_init_phy()
1695 netdev_warn(gp->dev, "GMAC PHY not responding !\n"); in gem_init_phy()
1699 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_init_phy()
1700 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_init_phy()
1704 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1705 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1707 } else if (gp->phy_type == phy_serialink) { in gem_init_phy()
1713 writel(val, gp->regs + PCS_DMODE); in gem_init_phy()
1716 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1717 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1719 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr); in gem_init_phy()
1722 if (gp->phy_mii.def && gp->phy_mii.def->ops->init) in gem_init_phy()
1723 gp->phy_mii.def->ops->init(&gp->phy_mii); in gem_init_phy()
1725 gem_pcs_reset(gp); in gem_init_phy()
1726 gem_pcs_reinit_adv(gp); in gem_init_phy()
1730 gp->timer_ticks = 0; in gem_init_phy()
1731 gp->lstate = link_down; in gem_init_phy()
1732 netif_carrier_off(gp->dev); in gem_init_phy()
1735 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1736 gp->phy_type == phy_mii_mdio1) in gem_init_phy()
1737 netdev_info(gp->dev, "Found %s PHY\n", in gem_init_phy()
1738 gp->phy_mii.def ? gp->phy_mii.def->name : "no"); in gem_init_phy()
1740 gem_begin_auto_negotiation(gp, NULL); in gem_init_phy()
1743 static void gem_init_dma(struct gem *gp) in gem_init_dma() argument
1745 u64 desc_dma = (u64) gp->gblock_dvma; in gem_init_dma()
1749 writel(val, gp->regs + TXDMA_CFG); in gem_init_dma()
1751 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); in gem_init_dma()
1752 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); in gem_init_dma()
1755 writel(0, gp->regs + TXDMA_KICK); in gem_init_dma()
1759 writel(val, gp->regs + RXDMA_CFG); in gem_init_dma()
1761 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_init_dma()
1762 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_init_dma()
1764 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_init_dma()
1766 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_init_dma()
1767 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_init_dma()
1768 writel(val, gp->regs + RXDMA_PTHRESH); in gem_init_dma()
1770 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_init_dma()
1773 gp->regs + RXDMA_BLANK); in gem_init_dma()
1777 gp->regs + RXDMA_BLANK); in gem_init_dma()
1780 static u32 gem_setup_multicast(struct gem *gp) in gem_setup_multicast() argument
1785 if ((gp->dev->flags & IFF_ALLMULTI) || in gem_setup_multicast()
1786 (netdev_mc_count(gp->dev) > 256)) { in gem_setup_multicast()
1788 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1790 } else if (gp->dev->flags & IFF_PROMISC) { in gem_setup_multicast()
1799 netdev_for_each_mc_addr(ha, gp->dev) { in gem_setup_multicast()
1805 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1812 static void gem_init_mac(struct gem *gp) in gem_init_mac() argument
1814 unsigned char *e = &gp->dev->dev_addr[0]; in gem_init_mac()
1816 writel(0x1bf0, gp->regs + MAC_SNDPAUSE); in gem_init_mac()
1818 writel(0x00, gp->regs + MAC_IPG0); in gem_init_mac()
1819 writel(0x08, gp->regs + MAC_IPG1); in gem_init_mac()
1820 writel(0x04, gp->regs + MAC_IPG2); in gem_init_mac()
1821 writel(0x40, gp->regs + MAC_STIME); in gem_init_mac()
1822 writel(0x40, gp->regs + MAC_MINFSZ); in gem_init_mac()
1825 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); in gem_init_mac()
1827 writel(0x07, gp->regs + MAC_PASIZE); in gem_init_mac()
1828 writel(0x04, gp->regs + MAC_JAMSIZE); in gem_init_mac()
1829 writel(0x10, gp->regs + MAC_ATTLIM); in gem_init_mac()
1830 writel(0x8808, gp->regs + MAC_MCTYPE); in gem_init_mac()
1832 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); in gem_init_mac()
1834 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_init_mac()
1835 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_init_mac()
1836 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_init_mac()
1838 writel(0, gp->regs + MAC_ADDR3); in gem_init_mac()
1839 writel(0, gp->regs + MAC_ADDR4); in gem_init_mac()
1840 writel(0, gp->regs + MAC_ADDR5); in gem_init_mac()
1842 writel(0x0001, gp->regs + MAC_ADDR6); in gem_init_mac()
1843 writel(0xc200, gp->regs + MAC_ADDR7); in gem_init_mac()
1844 writel(0x0180, gp->regs + MAC_ADDR8); in gem_init_mac()
1846 writel(0, gp->regs + MAC_AFILT0); in gem_init_mac()
1847 writel(0, gp->regs + MAC_AFILT1); in gem_init_mac()
1848 writel(0, gp->regs + MAC_AFILT2); in gem_init_mac()
1849 writel(0, gp->regs + MAC_AF21MSK); in gem_init_mac()
1850 writel(0, gp->regs + MAC_AF0MSK); in gem_init_mac()
1852 gp->mac_rx_cfg = gem_setup_multicast(gp); in gem_init_mac()
1854 gp->mac_rx_cfg |= MAC_RXCFG_SFCS; in gem_init_mac()
1856 writel(0, gp->regs + MAC_NCOLL); in gem_init_mac()
1857 writel(0, gp->regs + MAC_FASUCC); in gem_init_mac()
1858 writel(0, gp->regs + MAC_ECOLL); in gem_init_mac()
1859 writel(0, gp->regs + MAC_LCOLL); in gem_init_mac()
1860 writel(0, gp->regs + MAC_DTIMER); in gem_init_mac()
1861 writel(0, gp->regs + MAC_PATMPS); in gem_init_mac()
1862 writel(0, gp->regs + MAC_RFCTR); in gem_init_mac()
1863 writel(0, gp->regs + MAC_LERR); in gem_init_mac()
1864 writel(0, gp->regs + MAC_AERR); in gem_init_mac()
1865 writel(0, gp->regs + MAC_FCSERR); in gem_init_mac()
1866 writel(0, gp->regs + MAC_RXCVERR); in gem_init_mac()
1871 writel(0, gp->regs + MAC_TXCFG); in gem_init_mac()
1872 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); in gem_init_mac()
1873 writel(0, gp->regs + MAC_MCCFG); in gem_init_mac()
1874 writel(0, gp->regs + MAC_XIFCFG); in gem_init_mac()
1880 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); in gem_init_mac()
1881 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_init_mac()
1886 writel(0xffffffff, gp->regs + MAC_MCMASK); in gem_init_mac()
1890 if (gp->has_wol) in gem_init_mac()
1891 writel(0, gp->regs + WOL_WAKECSR); in gem_init_mac()
1894 static void gem_init_pause_thresholds(struct gem *gp) in gem_init_pause_thresholds() argument
1903 if (gp->rx_fifo_sz <= (2 * 1024)) { in gem_init_pause_thresholds()
1904 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; in gem_init_pause_thresholds()
1906 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; in gem_init_pause_thresholds()
1907 int off = (gp->rx_fifo_sz - (max_frame * 2)); in gem_init_pause_thresholds()
1910 gp->rx_pause_off = off; in gem_init_pause_thresholds()
1911 gp->rx_pause_on = on; in gem_init_pause_thresholds()
1919 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) in gem_init_pause_thresholds()
1926 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1931 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { in gem_init_pause_thresholds()
1934 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1938 static int gem_check_invariants(struct gem *gp) in gem_check_invariants() argument
1940 struct pci_dev *pdev = gp->pdev; in gem_check_invariants()
1948 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
1949 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
1950 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
1951 gp->swrst_base = 0; in gem_check_invariants()
1953 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1956 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
1957 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); in gem_check_invariants()
1958 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); in gem_check_invariants()
1964 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) in gem_check_invariants()
1965 gp->mii_phy_addr = 1; in gem_check_invariants()
1967 gp->mii_phy_addr = 0; in gem_check_invariants()
1972 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1991 gp->phy_type = phy_mii_mdio1; in gem_check_invariants()
1993 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
1995 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
1997 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
2002 p = of_get_property(gp->of_node, "shared-pins", NULL); in gem_check_invariants()
2004 gp->phy_type = phy_serdes; in gem_check_invariants()
2007 gp->phy_type = phy_serialink; in gem_check_invariants()
2009 if (gp->phy_type == phy_mii_mdio1 || in gem_check_invariants()
2010 gp->phy_type == phy_mii_mdio0) { in gem_check_invariants()
2014 gp->mii_phy_addr = i; in gem_check_invariants()
2015 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) in gem_check_invariants()
2023 gp->phy_type = phy_serdes; in gem_check_invariants()
2028 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
2029 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
2033 if (gp->tx_fifo_sz != (9 * 1024) || in gem_check_invariants()
2034 gp->rx_fifo_sz != (20 * 1024)) { in gem_check_invariants()
2036 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2039 gp->swrst_base = 0; in gem_check_invariants()
2041 if (gp->tx_fifo_sz != (2 * 1024) || in gem_check_invariants()
2042 gp->rx_fifo_sz != (2 * 1024)) { in gem_check_invariants()
2044 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2047 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; in gem_check_invariants()
2054 static void gem_reinit_chip(struct gem *gp) in gem_reinit_chip() argument
2057 gem_reset(gp); in gem_reinit_chip()
2060 gem_disable_ints(gp); in gem_reinit_chip()
2063 gem_init_rings(gp); in gem_reinit_chip()
2066 gem_init_pause_thresholds(gp); in gem_reinit_chip()
2069 gem_init_dma(gp); in gem_reinit_chip()
2070 gem_init_mac(gp); in gem_reinit_chip()
2074 static void gem_stop_phy(struct gem *gp, int wol) in gem_stop_phy() argument
2086 mifcfg = readl(gp->regs + MIF_CFG); in gem_stop_phy()
2088 writel(mifcfg, gp->regs + MIF_CFG); in gem_stop_phy()
2090 if (wol && gp->has_wol) { in gem_stop_phy()
2091 unsigned char *e = &gp->dev->dev_addr[0]; in gem_stop_phy()
2096 gp->regs + MAC_RXCFG); in gem_stop_phy()
2097 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); in gem_stop_phy()
2098 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); in gem_stop_phy()
2099 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); in gem_stop_phy()
2101 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); in gem_stop_phy()
2103 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) in gem_stop_phy()
2105 writel(csr, gp->regs + WOL_WAKECSR); in gem_stop_phy()
2107 writel(0, gp->regs + MAC_RXCFG); in gem_stop_phy()
2108 (void)readl(gp->regs + MAC_RXCFG); in gem_stop_phy()
2116 writel(0, gp->regs + MAC_TXCFG); in gem_stop_phy()
2117 writel(0, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2118 writel(0, gp->regs + TXDMA_CFG); in gem_stop_phy()
2119 writel(0, gp->regs + RXDMA_CFG); in gem_stop_phy()
2122 gem_reset(gp); in gem_stop_phy()
2123 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); in gem_stop_phy()
2124 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_stop_phy()
2126 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) in gem_stop_phy()
2127 gp->phy_mii.def->ops->suspend(&gp->phy_mii); in gem_stop_phy()
2132 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); in gem_stop_phy()
2133 writel(0, gp->regs + MIF_BBCLK); in gem_stop_phy()
2134 writel(0, gp->regs + MIF_BBDATA); in gem_stop_phy()
2135 writel(0, gp->regs + MIF_BBOENAB); in gem_stop_phy()
2136 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2137 (void) readl(gp->regs + MAC_XIFCFG); in gem_stop_phy()
2143 struct gem *gp = netdev_priv(dev); in gem_do_start() local
2147 gem_get_cell(gp); in gem_do_start()
2150 rc = pci_enable_device(gp->pdev); in gem_do_start()
2157 gem_put_cell(gp); in gem_do_start()
2160 pci_set_master(gp->pdev); in gem_do_start()
2163 gem_reinit_chip(gp); in gem_do_start()
2166 rc = request_irq(gp->pdev->irq, gem_interrupt, in gem_do_start()
2171 gem_reset(gp); in gem_do_start()
2172 gem_clean_rings(gp); in gem_do_start()
2173 gem_put_cell(gp); in gem_do_start()
2183 gem_netif_start(gp); in gem_do_start()
2189 gem_init_phy(gp); in gem_do_start()
2196 struct gem *gp = netdev_priv(dev); in gem_do_stop() local
2199 gem_netif_stop(gp); in gem_do_stop()
2206 gem_disable_ints(gp); in gem_do_stop()
2209 del_timer_sync(&gp->link_timer); in gem_do_stop()
2220 gp->reset_task_pending = 0; in gem_do_stop()
2223 gem_stop_dma(gp); in gem_do_stop()
2226 gem_reset(gp); in gem_do_stop()
2230 gem_clean_rings(gp); in gem_do_stop()
2233 free_irq(gp->pdev->irq, (void *) dev); in gem_do_stop()
2236 gem_stop_phy(gp, wol); in gem_do_stop()
2239 pci_disable_device(gp->pdev); in gem_do_stop()
2243 gem_put_cell(gp); in gem_do_stop()
2248 struct gem *gp = container_of(work, struct gem, reset_task); in gem_reset_task() local
2258 if (!netif_device_present(gp->dev) || in gem_reset_task()
2259 !netif_running(gp->dev) || in gem_reset_task()
2260 !gp->reset_task_pending) { in gem_reset_task()
2266 del_timer_sync(&gp->link_timer); in gem_reset_task()
2269 gem_netif_stop(gp); in gem_reset_task()
2272 gem_reinit_chip(gp); in gem_reset_task()
2273 if (gp->lstate == link_up) in gem_reset_task()
2274 gem_set_link_modes(gp); in gem_reset_task()
2277 gem_netif_start(gp); in gem_reset_task()
2280 gp->reset_task_pending = 0; in gem_reset_task()
2285 if (gp->lstate != link_up) in gem_reset_task()
2286 gem_begin_auto_negotiation(gp, NULL); in gem_reset_task()
2288 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_reset_task()
2315 struct gem *gp = netdev_priv(dev); in gem_suspend() local
2331 (gp->wake_on_lan && netif_running(dev)) ? in gem_suspend()
2340 gp->asleep_wol = !!gp->wake_on_lan; in gem_suspend()
2341 gem_do_stop(dev, gp->asleep_wol); in gem_suspend()
2352 struct gem *gp = netdev_priv(dev); in gem_resume() local
2374 if (gp->asleep_wol) in gem_resume()
2375 gem_put_cell(gp); in gem_resume()
2386 struct gem *gp = netdev_priv(dev); in gem_get_stats() local
2399 if (WARN_ON(!gp->cell_enabled)) in gem_get_stats()
2402 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR); in gem_get_stats()
2403 writel(0, gp->regs + MAC_FCSERR); in gem_get_stats()
2405 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR); in gem_get_stats()
2406 writel(0, gp->regs + MAC_AERR); in gem_get_stats()
2408 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR); in gem_get_stats()
2409 writel(0, gp->regs + MAC_LERR); in gem_get_stats()
2411 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL); in gem_get_stats()
2413 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL)); in gem_get_stats()
2414 writel(0, gp->regs + MAC_ECOLL); in gem_get_stats()
2415 writel(0, gp->regs + MAC_LCOLL); in gem_get_stats()
2423 struct gem *gp = netdev_priv(dev); in gem_set_mac_address() local
2436 if (WARN_ON(!gp->cell_enabled)) in gem_set_mac_address()
2439 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_set_mac_address()
2440 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_set_mac_address()
2441 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_set_mac_address()
2448 struct gem *gp = netdev_priv(dev); in gem_set_multicast() local
2456 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled)) in gem_set_multicast()
2459 rxcfg = readl(gp->regs + MAC_RXCFG); in gem_set_multicast()
2460 rxcfg_new = gem_setup_multicast(gp); in gem_set_multicast()
2464 gp->mac_rx_cfg = rxcfg_new; in gem_set_multicast()
2466 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_set_multicast()
2467 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { in gem_set_multicast()
2476 writel(rxcfg, gp->regs + MAC_RXCFG); in gem_set_multicast()
2489 struct gem *gp = netdev_priv(dev); in gem_change_mtu() local
2501 if (WARN_ON(!gp->cell_enabled)) in gem_change_mtu()
2504 gem_netif_stop(gp); in gem_change_mtu()
2505 gem_reinit_chip(gp); in gem_change_mtu()
2506 if (gp->lstate == link_up) in gem_change_mtu()
2507 gem_set_link_modes(gp); in gem_change_mtu()
2508 gem_netif_start(gp); in gem_change_mtu()
2515 struct gem *gp = netdev_priv(dev); in gem_get_drvinfo() local
2519 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info)); in gem_get_drvinfo()
2524 struct gem *gp = netdev_priv(dev); in gem_get_settings() local
2526 if (gp->phy_type == phy_mii_mdio0 || in gem_get_settings()
2527 gp->phy_type == phy_mii_mdio1) { in gem_get_settings()
2528 if (gp->phy_mii.def) in gem_get_settings()
2529 cmd->supported = gp->phy_mii.def->features; in gem_get_settings()
2540 cmd->autoneg = gp->want_autoneg; in gem_get_settings()
2541 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed); in gem_get_settings()
2542 cmd->duplex = gp->phy_mii.duplex; in gem_get_settings()
2543 cmd->advertising = gp->phy_mii.advertising; in gem_get_settings()
2562 if (gp->phy_type == phy_serdes) { in gem_get_settings()
2570 if (gp->lstate == link_up) in gem_get_settings()
2583 struct gem *gp = netdev_priv(dev); in gem_set_settings() local
2604 if (netif_device_present(gp->dev)) { in gem_set_settings()
2605 del_timer_sync(&gp->link_timer); in gem_set_settings()
2606 gem_begin_auto_negotiation(gp, cmd); in gem_set_settings()
2614 struct gem *gp = netdev_priv(dev); in gem_nway_reset() local
2616 if (!gp->want_autoneg) in gem_nway_reset()
2620 if (netif_device_present(gp->dev)) { in gem_nway_reset()
2621 del_timer_sync(&gp->link_timer); in gem_nway_reset()
2622 gem_begin_auto_negotiation(gp, NULL); in gem_nway_reset()
2630 struct gem *gp = netdev_priv(dev); in gem_get_msglevel() local
2631 return gp->msg_enable; in gem_get_msglevel()
2636 struct gem *gp = netdev_priv(dev); in gem_set_msglevel() local
2637 gp->msg_enable = value; in gem_set_msglevel()
2648 struct gem *gp = netdev_priv(dev); in gem_get_wol() local
2651 if (gp->has_wol) { in gem_get_wol()
2653 wol->wolopts = gp->wake_on_lan; in gem_get_wol()
2662 struct gem *gp = netdev_priv(dev); in gem_set_wol() local
2664 if (!gp->has_wol) in gem_set_wol()
2666 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; in gem_set_wol()
2684 struct gem *gp = netdev_priv(dev); in gem_ioctl() local
2695 data->phy_id = gp->mii_phy_addr; in gem_ioctl()
2699 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f, in gem_ioctl()
2705 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, in gem_ioctl()
2765 static int gem_get_device_address(struct gem *gp) in gem_get_device_address() argument
2768 struct net_device *dev = gp->dev; in gem_get_device_address()
2771 addr = of_get_property(gp->of_node, "local-mac-address", NULL); in gem_get_device_address()
2783 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); in gem_get_device_address()
2793 struct gem *gp = netdev_priv(dev); in gem_remove_one() local
2798 cancel_work_sync(&gp->reset_task); in gem_remove_one()
2803 gp->init_block, in gem_remove_one()
2804 gp->gblock_dvma); in gem_remove_one()
2805 iounmap(gp->regs); in gem_remove_one()
2831 struct gem *gp; in gem_init_one() local
2880 dev = alloc_etherdev(sizeof(*gp)); in gem_init_one()
2887 gp = netdev_priv(dev); in gem_init_one()
2895 gp->pdev = pdev; in gem_init_one()
2896 gp->dev = dev; in gem_init_one()
2898 gp->msg_enable = DEFAULT_MSG; in gem_init_one()
2900 init_timer(&gp->link_timer); in gem_init_one()
2901 gp->link_timer.function = gem_link_timer; in gem_init_one()
2902 gp->link_timer.data = (unsigned long) gp; in gem_init_one()
2904 INIT_WORK(&gp->reset_task, gem_reset_task); in gem_init_one()
2906 gp->lstate = link_down; in gem_init_one()
2907 gp->timer_ticks = 0; in gem_init_one()
2910 gp->regs = ioremap(gemreg_base, gemreg_len); in gem_init_one()
2911 if (!gp->regs) { in gem_init_one()
2921 gp->of_node = pci_device_to_OF_node(pdev); in gem_init_one()
2926 gp->has_wol = 1; in gem_init_one()
2929 gem_get_cell(gp); in gem_init_one()
2932 gem_reset(gp); in gem_init_one()
2935 gp->phy_mii.dev = dev; in gem_init_one()
2936 gp->phy_mii.mdio_read = _sungem_phy_read; in gem_init_one()
2937 gp->phy_mii.mdio_write = _sungem_phy_write; in gem_init_one()
2939 gp->phy_mii.platform_data = gp->of_node; in gem_init_one()
2942 gp->want_autoneg = 1; in gem_init_one()
2945 if (gem_check_invariants(gp)) { in gem_init_one()
2953 gp->init_block = (struct gem_init_block *) in gem_init_one()
2955 &gp->gblock_dvma); in gem_init_one()
2956 if (!gp->init_block) { in gem_init_one()
2962 err = gem_get_device_address(gp); in gem_init_one()
2967 netif_napi_add(dev, &gp->napi, gem_poll, 64); in gem_init_one()
2992 gem_put_cell(gp); in gem_init_one()
3002 gem_put_cell(gp); in gem_init_one()
3003 iounmap(gp->regs); in gem_init_one()