Lines Matching refs:SMC_REG
450 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
469 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
488 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
505 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
510 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
515 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
541 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
553 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
558 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
559 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
560 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
565 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
570 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
583 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
597 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
602 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
608 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
613 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
616 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
620 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
628 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
633 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
638 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
651 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
652 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
653 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
654 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
659 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
670 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
676 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
683 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
807 #define SMC_REG(lp, reg, bank) \ macro
818 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) macro
839 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
919 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
941 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
959 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \