123 static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)  in SMC_inl()  argument
125 	void __iomem *ioaddr = lp->base + reg;  in SMC_inl()
127 	if (lp->cfg.flags & SMC911X_USE_32BIT)  in SMC_inl()
130 	if (lp->cfg.flags & SMC911X_USE_16BIT)  in SMC_inl()
136 static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,  in SMC_outl()  argument
139 	void __iomem *ioaddr = lp->base + reg;  in SMC_outl()
141 	if (lp->cfg.flags & SMC911X_USE_32BIT) {  in SMC_outl()
146 	if (lp->cfg.flags & SMC911X_USE_16BIT) {  in SMC_outl()
155 static inline void SMC_insl(struct smc911x_local *lp, int reg,  in SMC_insl()  argument
158 	void __iomem *ioaddr = lp->base + reg;  in SMC_insl()
160 	if (lp->cfg.flags & SMC911X_USE_32BIT) {  in SMC_insl()
165 	if (lp->cfg.flags & SMC911X_USE_16BIT) {  in SMC_insl()
173 static inline void SMC_outsl(struct smc911x_local *lp, int reg,  in SMC_outsl()  argument
176 	void __iomem *ioaddr = lp->base + reg;  in SMC_outsl()
178 	if (lp->cfg.flags & SMC911X_USE_32BIT) {  in SMC_outsl()
183 	if (lp->cfg.flags & SMC911X_USE_16BIT) {  in SMC_outsl()
192 #define SMC_inl(lp, r)		 ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))  argument
193 #define SMC_outl(v, lp, r) 			 \  argument
195 		 writew(v & 0xFFFF, (lp)->base + (r));	 \
196 		 writew(v >> 16, (lp)->base + (r) + 2); \
198 #define SMC_insl(lp, r, p, l)	 ioread16_rep((short*)((lp)->base + (r)), p, l*2)  argument
199 #define SMC_outsl(lp, r, p, l)	 iowrite16_rep((short*)((lp)->base + (r)), p, l*2)  argument
202 #define SMC_inl(lp, r)		 readl((lp)->base + (r))  argument
203 #define SMC_outl(v, lp, r)	 writel(v, (lp)->base + (r))  argument
204 #define SMC_insl(lp, r, p, l)	 ioread32_rep((int*)((lp)->base + (r)), p, l)  argument
205 #define SMC_outsl(lp, r, p, l)	 iowrite32_rep((int*)((lp)->base + (r)), p, l)  argument
244 #define SMC_insl(lp, r, p, l) \  argument
245 	smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
248 smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,  in smc_pxa_dma_insl()  argument
253 		*((u32 *)buf) = SMC_inl(lp, reg);  in smc_pxa_dma_insl()
259 	rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_insl()
272 #define SMC_outsl(lp, r, p, l) \  argument
273 	 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
276 smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,  in smc_pxa_dma_outsl()  argument
281 		SMC_outl(*((u32 *)buf), lp, reg);  in smc_pxa_dma_outsl()
287 	tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);  in smc_pxa_dma_outsl()
714 #define SMC_PUSH_DATA(lp, p, l)	SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )  argument
715 #define SMC_PULL_DATA(lp, p, l)	SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )  argument
716 #define SMC_SET_TX_FIFO(lp, x) 	SMC_outl( x, lp, TX_DATA_FIFO )  argument
717 #define SMC_GET_RX_FIFO(lp)	SMC_inl( lp, RX_DATA_FIFO )  argument
721 #define SMC_GET_TX_STS_FIFO(lp)		SMC_inl( lp, TX_STATUS_FIFO )  argument
722 #define SMC_GET_RX_STS_FIFO(lp)		SMC_inl( lp, RX_STATUS_FIFO )  argument
723 #define SMC_GET_RX_STS_FIFO_PEEK(lp)	SMC_inl( lp, RX_STATUS_FIFO_PEEK )  argument
724 #define SMC_GET_PN(lp)			(SMC_inl( lp, ID_REV ) >> 16)  argument
725 #define SMC_GET_REV(lp)			(SMC_inl( lp, ID_REV ) & 0xFFFF)  argument
726 #define SMC_GET_IRQ_CFG(lp)		SMC_inl( lp, INT_CFG )  argument
727 #define SMC_SET_IRQ_CFG(lp, x)		SMC_outl( x, lp, INT_CFG )  argument
728 #define SMC_GET_INT(lp)			SMC_inl( lp, INT_STS )  argument
729 #define SMC_ACK_INT(lp, x)			SMC_outl( x, lp, INT_STS )  argument
730 #define SMC_GET_INT_EN(lp)		SMC_inl( lp, INT_EN )  argument
731 #define SMC_SET_INT_EN(lp, x)		SMC_outl( x, lp, INT_EN )  argument
732 #define SMC_GET_BYTE_TEST(lp)		SMC_inl( lp, BYTE_TEST )  argument
733 #define SMC_SET_BYTE_TEST(lp, x)		SMC_outl( x, lp, BYTE_TEST )  argument
734 #define SMC_GET_FIFO_INT(lp)		SMC_inl( lp, FIFO_INT )  argument
735 #define SMC_SET_FIFO_INT(lp, x)		SMC_outl( x, lp, FIFO_INT )  argument
736 #define SMC_SET_FIFO_TDA(lp, x)					\  argument
741 		__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);	\
742 		SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 );	\
745 #define SMC_SET_FIFO_TSL(lp, x)					\  argument
750 		__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);	\
751 		SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));	\
754 #define SMC_SET_FIFO_RSA(lp, x)					\  argument
759 		__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);	\
760 		SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));	\
763 #define SMC_SET_FIFO_RSL(lp, x)					\  argument
768 		__mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;	\
769 		SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));	\
772 #define SMC_GET_RX_CFG(lp)		SMC_inl( lp, RX_CFG )  argument
773 #define SMC_SET_RX_CFG(lp, x)		SMC_outl( x, lp, RX_CFG )  argument
774 #define SMC_GET_TX_CFG(lp)		SMC_inl( lp, TX_CFG )  argument
775 #define SMC_SET_TX_CFG(lp, x)		SMC_outl( x, lp, TX_CFG )  argument
776 #define SMC_GET_HW_CFG(lp)		SMC_inl( lp, HW_CFG )  argument
777 #define SMC_SET_HW_CFG(lp, x)		SMC_outl( x, lp, HW_CFG )  argument
778 #define SMC_GET_RX_DP_CTRL(lp)		SMC_inl( lp, RX_DP_CTRL )  argument
779 #define SMC_SET_RX_DP_CTRL(lp, x)		SMC_outl( x, lp, RX_DP_CTRL )  argument
780 #define SMC_GET_PMT_CTRL(lp)		SMC_inl( lp, PMT_CTRL )  argument
781 #define SMC_SET_PMT_CTRL(lp, x)		SMC_outl( x, lp, PMT_CTRL )  argument
782 #define SMC_GET_GPIO_CFG(lp)		SMC_inl( lp, GPIO_CFG )  argument
783 #define SMC_SET_GPIO_CFG(lp, x)		SMC_outl( x, lp, GPIO_CFG )  argument
784 #define SMC_GET_RX_FIFO_INF(lp)		SMC_inl( lp, RX_FIFO_INF )  argument
785 #define SMC_SET_RX_FIFO_INF(lp, x)		SMC_outl( x, lp, RX_FIFO_INF )  argument
786 #define SMC_GET_TX_FIFO_INF(lp)		SMC_inl( lp, TX_FIFO_INF )  argument
787 #define SMC_SET_TX_FIFO_INF(lp, x)		SMC_outl( x, lp, TX_FIFO_INF )  argument
788 #define SMC_GET_GPT_CFG(lp)		SMC_inl( lp, GPT_CFG )  argument
789 #define SMC_SET_GPT_CFG(lp, x)		SMC_outl( x, lp, GPT_CFG )  argument
790 #define SMC_GET_RX_DROP(lp)		SMC_inl( lp, RX_DROP )  argument
791 #define SMC_SET_RX_DROP(lp, x)		SMC_outl( x, lp, RX_DROP )  argument
792 #define SMC_GET_MAC_CMD(lp)		SMC_inl( lp, MAC_CSR_CMD )  argument
793 #define SMC_SET_MAC_CMD(lp, x)		SMC_outl( x, lp, MAC_CSR_CMD )  argument
794 #define SMC_GET_MAC_DATA(lp)		SMC_inl( lp, MAC_CSR_DATA )  argument
795 #define SMC_SET_MAC_DATA(lp, x)		SMC_outl( x, lp, MAC_CSR_DATA )  argument
796 #define SMC_GET_AFC_CFG(lp)		SMC_inl( lp, AFC_CFG )  argument
797 #define SMC_SET_AFC_CFG(lp, x)		SMC_outl( x, lp, AFC_CFG )  argument
798 #define SMC_GET_E2P_CMD(lp)		SMC_inl( lp, E2P_CMD )  argument
799 #define SMC_SET_E2P_CMD(lp, x)		SMC_outl( x, lp, E2P_CMD )  argument
800 #define SMC_GET_E2P_DATA(lp)		SMC_inl( lp, E2P_DATA )  argument
801 #define SMC_SET_E2P_DATA(lp, x)		SMC_outl( x, lp, E2P_DATA )  argument
804 #define SMC_GET_MAC_CSR(lp,a,v)						\  argument
806 		while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\
807 		SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |		\
809 		while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\
810 		v = SMC_GET_MAC_DATA((lp));			       	\
812 #define SMC_SET_MAC_CSR(lp,a,v)						\  argument
814 		while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\
815 		SMC_SET_MAC_DATA((lp), v);				\
816 		SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );	\
817 		while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\
819 #define SMC_GET_MAC_CR(lp, x)	SMC_GET_MAC_CSR( (lp), MAC_CR, x )  argument
820 #define SMC_SET_MAC_CR(lp, x)	SMC_SET_MAC_CSR( (lp), MAC_CR, x )  argument
821 #define SMC_GET_ADDRH(lp, x)	SMC_GET_MAC_CSR( (lp), ADDRH, x )  argument
822 #define SMC_SET_ADDRH(lp, x)	SMC_SET_MAC_CSR( (lp), ADDRH, x )  argument
823 #define SMC_GET_ADDRL(lp, x)	SMC_GET_MAC_CSR( (lp), ADDRL, x )  argument
824 #define SMC_SET_ADDRL(lp, x)	SMC_SET_MAC_CSR( (lp), ADDRL, x )  argument
825 #define SMC_GET_HASHH(lp, x)	SMC_GET_MAC_CSR( (lp), HASHH, x )  argument
826 #define SMC_SET_HASHH(lp, x)	SMC_SET_MAC_CSR( (lp), HASHH, x )  argument
827 #define SMC_GET_HASHL(lp, x)	SMC_GET_MAC_CSR( (lp), HASHL, x )  argument
828 #define SMC_SET_HASHL(lp, x)	SMC_SET_MAC_CSR( (lp), HASHL, x )  argument
829 #define SMC_GET_MII_ACC(lp, x)	SMC_GET_MAC_CSR( (lp), MII_ACC, x )  argument
830 #define SMC_SET_MII_ACC(lp, x)	SMC_SET_MAC_CSR( (lp), MII_ACC, x )  argument
831 #define SMC_GET_MII_DATA(lp, x)	SMC_GET_MAC_CSR( (lp), MII_DATA, x )  argument
832 #define SMC_SET_MII_DATA(lp, x)	SMC_SET_MAC_CSR( (lp), MII_DATA, x )  argument
833 #define SMC_GET_FLOW(lp, x)		SMC_GET_MAC_CSR( (lp), FLOW, x )  argument
834 #define SMC_SET_FLOW(lp, x)		SMC_SET_MAC_CSR( (lp), FLOW, x )  argument
835 #define SMC_GET_VLAN1(lp, x)	SMC_GET_MAC_CSR( (lp), VLAN1, x )  argument
836 #define SMC_SET_VLAN1(lp, x)	SMC_SET_MAC_CSR( (lp), VLAN1, x )  argument
837 #define SMC_GET_VLAN2(lp, x)	SMC_GET_MAC_CSR( (lp), VLAN2, x )  argument
838 #define SMC_SET_VLAN2(lp, x)	SMC_SET_MAC_CSR( (lp), VLAN2, x )  argument
839 #define SMC_SET_WUFF(lp, x)		SMC_SET_MAC_CSR( (lp), WUFF, x )  argument
840 #define SMC_GET_WUCSR(lp, x)	SMC_GET_MAC_CSR( (lp), WUCSR, x )  argument
841 #define SMC_SET_WUCSR(lp, x)	SMC_SET_MAC_CSR( (lp), WUCSR, x )  argument
844 #define SMC_GET_MII(lp,a,phy,v)					\  argument
848 			SMC_GET_MII_ACC((lp), __v);			\
850 		SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) |	\
853 			SMC_GET_MII_ACC( (lp), __v);			\
855 		SMC_GET_MII_DATA((lp), v);				\
857 #define SMC_SET_MII(lp,a,phy,v)					\  argument
861 			SMC_GET_MII_ACC((lp), __v);			\
863 		SMC_SET_MII_DATA((lp), v);				\
864 		SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) |	\
868 			SMC_GET_MII_ACC((lp), __v);			\
871 #define SMC_GET_PHY_BMCR(lp,phy,x)		SMC_GET_MII( (lp), MII_BMCR, phy, x )  argument
872 #define SMC_SET_PHY_BMCR(lp,phy,x)		SMC_SET_MII( (lp), MII_BMCR, phy, x )  argument
873 #define SMC_GET_PHY_BMSR(lp,phy,x)		SMC_GET_MII( (lp), MII_BMSR, phy, x )  argument
874 #define SMC_GET_PHY_ID1(lp,phy,x)		SMC_GET_MII( (lp), MII_PHYSID1, phy, x )  argument
875 #define SMC_GET_PHY_ID2(lp,phy,x)		SMC_GET_MII( (lp), MII_PHYSID2, phy, x )  argument
876 #define SMC_GET_PHY_MII_ADV(lp,phy,x)	SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )  argument
877 #define SMC_SET_PHY_MII_ADV(lp,phy,x)	SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )  argument
878 #define SMC_GET_PHY_MII_LPA(lp,phy,x)	SMC_GET_MII( (lp), MII_LPA, phy, x )  argument
879 #define SMC_SET_PHY_MII_LPA(lp,phy,x)	SMC_SET_MII( (lp), MII_LPA, phy, x )  argument
880 #define SMC_GET_PHY_CTRL_STS(lp,phy,x)	SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )  argument
881 #define SMC_SET_PHY_CTRL_STS(lp,phy,x)	SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )  argument
882 #define SMC_GET_PHY_INT_SRC(lp,phy,x)	SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )  argument
883 #define SMC_SET_PHY_INT_SRC(lp,phy,x)	SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )  argument
884 #define SMC_GET_PHY_INT_MASK(lp,phy,x)	SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )  argument
885 #define SMC_SET_PHY_INT_MASK(lp,phy,x)	SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )  argument
886 #define SMC_GET_PHY_SPECIAL(lp,phy,x)	SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )  argument
893 #define SMC_GET_MAC_ADDR(lp, addr)				\  argument
897 		SMC_GET_MAC_CSR((lp), ADDRL, __v);			\
900 		SMC_GET_MAC_CSR((lp), ADDRH, __v);			\
905 #define SMC_SET_MAC_ADDR(lp, addr)				\  argument
907 		 SMC_SET_MAC_CSR((lp), ADDRL,				\
912 		 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
916 #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)				\  argument
918 		while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\
919 		SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );		\
920 		while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);	\