207 #define sw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
337 	sw32(cr, rfcrSave | RELOAD);  in sis635_get_mac_addr()
338 	sw32(cr, 0);  in sis635_get_mac_addr()
341 	sw32(rfcr, rfcrSave & ~RFEN);  in sis635_get_mac_addr()
345 		sw32(rfcr, (i << RFADDR_shift));  in sis635_get_mac_addr()
350 	sw32(rfcr, rfcrSave | RFEN);  in sis635_get_mac_addr()
378 	sw32(mear, EEREQ);  in sis96x_get_mac_addr()
393 	sw32(mear, EEDONE);  in sis96x_get_mac_addr()
538 		sw32(cr, ACCESSMODE | sr32(cr));  in sis900_probe()
820 	sw32(mear, 0);  in read_eeprom()
822 	sw32(mear, EECS);  in read_eeprom()
829 		sw32(mear, dataval);  in read_eeprom()
831 		sw32(mear, dataval | EECLK);  in read_eeprom()
834 	sw32(mear, EECS);  in read_eeprom()
839 		sw32(mear, EECS);  in read_eeprom()
841 		sw32(mear, EECS | EECLK);  in read_eeprom()
848 	sw32(mear, 0);  in read_eeprom()
863 	sw32(mear, MDIO | MDDIR);  in mdio_idle()
865 	sw32(mear, MDIO | MDDIR | MDC);  in mdio_idle()
875 		sw32(mear, MDDIR | MDIO);  in mdio_reset()
877 		sw32(mear, MDDIR | MDIO | MDC);  in mdio_reset()
907 		sw32(mear, dataval);  in mdio_read()
909 		sw32(mear, dataval | MDC);  in mdio_read()
915 		sw32(mear, 0);  in mdio_read()
918 		sw32(mear, MDC);  in mdio_read()
921 	sw32(mear, 0x00);  in mdio_read()
964 		sw32(mear, dataval);  in mdio_write()
966 		sw32(mear, dataval | MDC);  in mdio_write()
978 	sw32(mear, 0x00);  in mdio_write()
1061 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);  in sis900_open()
1062 	sw32(cr, RxENA | sr32(cr));  in sis900_open()
1063 	sw32(ier, IE);  in sis900_open()
1097 	sw32(rfcr, rfcrSave & ~RFEN);  in sis900_init_rxfilter()
1103 		sw32(rfcr, i << RFADDR_shift);  in sis900_init_rxfilter()
1104 		sw32(rfdr, w);  in sis900_init_rxfilter()
1113 	sw32(rfcr, rfcrSave | RFEN);  in sis900_init_rxfilter()
1143 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_init_tx_ring()
1202 	sw32(rxdp, sis_priv->rx_ring_dma);  in sis900_init_rx_ring()
1376 		sw32(cfg, ~EXD & sr32(cfg));  in sis900_check_mode()
1380 		sw32(cfg, EXD | sr32(cfg));  in sis900_check_mode()
1434 	sw32(txcfg, tx_flags);  in sis900_set_mode()
1435 	sw32(rxcfg, rx_flags);  in sis900_set_mode()
1552 	sw32(imr, 0x0000);  in sis900_tx_timeout()
1581 	sw32(txdp, sis_priv->tx_ring_dma);  in sis900_tx_timeout()
1584 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);  in sis900_tx_timeout()
1625 	sw32(cr, TxENA | sr32(cr));  in sis900_start_xmit()
1873 	sw32(cr , RxENA | sr32(cr));  in sis900_rx()
1967 	sw32(imr, 0x0000);  in sis900_close()
1968 	sw32(ier, 0x0000);  in sis900_close()
1971 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_close()
2087 		sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2102 	sw32(pmctrl, pmctrl_bits);  in sis900_set_wol()
2347 		sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);  in set_rx_mode()
2348 		sw32(rfdr, mc_filter[i]);  in set_rx_mode()
2351 	sw32(rfcr, RFEN | rx_mode);  in set_rx_mode()
2359 		sw32(cr, cr_saved | TxDIS | RxDIS);  in set_rx_mode()
2361 		sw32(txcfg, sr32(txcfg) | TxMLB);  in set_rx_mode()
2362 		sw32(rxcfg, sr32(rxcfg) | RxATX);  in set_rx_mode()
2364 		sw32(cr, cr_saved);  in set_rx_mode()
2384 	sw32(ier, 0);  in sis900_reset()
2385 	sw32(imr, 0);  in sis900_reset()
2386 	sw32(rfcr, 0);  in sis900_reset()
2388 	sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));  in sis900_reset()
2396 		sw32(cfg, PESEL | RND_CNT);  in sis900_reset()
2398 		sw32(cfg, PESEL);  in sis900_reset()
2446 	sw32(cr, RxDIS | TxDIS | sr32(cr));  in sis900_suspend()
2479 	sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE);  in sis900_resume()
2480 	sw32(cr, RxENA | sr32(cr));  in sis900_resume()
2481 	sw32(ier, IE);  in sis900_resume()