104 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))  macro
978 	RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
990 	RTL_W32(GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
1003 	RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);  in r8168_mac_ocp_write()
1013 	RTL_W32(OCPDR, reg << 15);  in r8168_mac_ocp_read()
1067 	RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
1082 	RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
1107 	RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));  in r8168dp_1_mdio_access()
1108 	RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);  in r8168dp_1_mdio_access()
1109 	RTL_W32(EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_access()
1127 	RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);  in r8168dp_1_mdio_read()
1128 	RTL_W32(EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_read()
1138 	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
1143 	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
1220 	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1232 	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1251 	RTL_W32(ERIDR, val);  in rtl_eri_write()
1252 	RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);  in rtl_eri_write()
1261 	RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);  in rtl_eri_read()
1280 	RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1312 	RTL_W32(OCPDR, data);  in r8168dp_ocp_write()
1313 	RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1509 	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1589 	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);  in rtl8169_tbi_reset_enable()
1888 		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));  in rtl8169_set_speed_tbi()
1890 		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);  in rtl8169_set_speed_tbi()
2040 	RTL_W32(RxConfig, rx_config);  in __rtl8169_set_features()
2209 	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);  in rtl8169_update_counters()
2211 	RTL_W32(CounterAddrLow, cmd);  in rtl8169_update_counters()
2212 	RTL_W32(CounterAddrLow, cmd | CounterDump);  in rtl8169_update_counters()
2217 	RTL_W32(CounterAddrLow, 0);  in rtl8169_update_counters()
2218 	RTL_W32(CounterAddrHigh, 0);  in rtl8169_update_counters()
4375 	RTL_W32(MAC4, addr[4] | addr[5] << 8);  in rtl_rar_set()
4378 	RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);  in rtl_rar_set()
4531 		RTL_W32(RxConfig, RTL_R32(RxConfig) |  in rtl_wol_suspend_quirk()
4854 		RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
4865 		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
4868 		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
4881 		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
4884 		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
5120 	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
5182 	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |  in rtl_set_rx_tx_config_registers()
5203 	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
5204 	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
5205 	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
5206 	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
5243 			RTL_W32(0x7c, p->val);  in rtl8169_set_magic_reg()
5296 	RTL_W32(MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
5297 	RTL_W32(MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
5299 	RTL_W32(RxConfig, tmp);  in rtl_set_rx_mode()
5366 	RTL_W32(RxMissed, 0);  in rtl_hw_start_8169()
5414 	RTL_W32(CSIDR, value);  in r8169_csi_write()
5415 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in r8169_csi_write()
5425 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |  in r8169_csi_read()
5436 	RTL_W32(CSIDR, value);  in r8402_csi_write()
5437 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in r8402_csi_write()
5448 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |  in r8402_csi_read()
5459 	RTL_W32(CSIDR, value);  in r8411_csi_write()
5460 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in r8411_csi_write()
5471 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |  in r8411_csi_read()
5806 	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
5807 	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
5841 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168e_2()
5848 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
5876 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168f()
5879 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);  in rtl_hw_start_8168f()
5925 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168g()
5940 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168g()
6030 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168h_1()
6050 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168h_1()
6115 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8168ep()
6133 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168ep()
6444 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
6447 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
6474 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8402()
6476 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);  in rtl_hw_start_8402()
6499 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);  in rtl_hw_start_8106()
6501 	RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
7507 	RTL_W32(RxMissed, 0);  in rtl8169_rx_missed()
7998 	RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);  in rtl_hw_init_8168g()