167 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_set_rx_irq()
179 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_set_tx_irq()
246 		cvmx_write_csr(p->mix + MIX_IRING2, 1);  in octeon_mgmt_rx_fill_ring()
282 		cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);  in octeon_mgmt_clean_tx_buffers()
299 			cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0);  in octeon_mgmt_clean_tx_buffers()
469 	cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);  in octeon_mgmt_receive_one()
521 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_reset_hw()
526 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_reset_hw()
608 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);  in octeon_mgmt_set_rx_filtering()
615 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);  in octeon_mgmt_set_rx_filtering()
617 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]);  in octeon_mgmt_set_rx_filtering()
618 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]);  in octeon_mgmt_set_rx_filtering()
619 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]);  in octeon_mgmt_set_rx_filtering()
620 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]);  in octeon_mgmt_set_rx_filtering()
621 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]);  in octeon_mgmt_set_rx_filtering()
622 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]);  in octeon_mgmt_set_rx_filtering()
623 	cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask);  in octeon_mgmt_set_rx_filtering()
627 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);  in octeon_mgmt_set_rx_filtering()
661 	cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs);  in octeon_mgmt_change_mtu()
662 	cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER,  in octeon_mgmt_change_mtu()
677 	cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);  in octeon_mgmt_interrupt()
718 				cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);  in octeon_mgmt_ioctl_hwtstamp()
732 			cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64);  in octeon_mgmt_ioctl_hwtstamp()
753 		cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_ioctl_hwtstamp()
774 			cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_ioctl_hwtstamp()
811 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_disable_link()
834 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_enable_link()
883 	cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);  in octeon_mgmt_update_link()
902 		cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);  in octeon_mgmt_update_link()
1016 		cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_open()
1025 		cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);  in octeon_mgmt_open()
1044 		cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);  in octeon_mgmt_open()
1050 	cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);  in octeon_mgmt_open()
1055 	cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);  in octeon_mgmt_open()
1074 	cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);  in octeon_mgmt_open()
1090 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1105 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1116 		cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);  in octeon_mgmt_open()
1124 		cvmx_write_csr(p->agl_prt_ctl,	agl_prtx_ctl.u64);  in octeon_mgmt_open()
1137 		cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);  in octeon_mgmt_open()
1144 	cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1);  in octeon_mgmt_open()
1145 	cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0);  in octeon_mgmt_open()
1146 	cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0);  in octeon_mgmt_open()
1148 	cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1);  in octeon_mgmt_open()
1149 	cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0);  in octeon_mgmt_open()
1150 	cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0);  in octeon_mgmt_open()
1153 	cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));  in octeon_mgmt_open()
1164 	cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);  in octeon_mgmt_open()
1169 	cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);  in octeon_mgmt_open()
1175 	cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);  in octeon_mgmt_open()
1204 	cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);  in octeon_mgmt_open()
1321 	cvmx_write_csr(p->mix + MIX_ORING2, 1);  in octeon_mgmt_xmit()