957 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);  in mlx4_QUERY_DEV_CAP()
1008 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,  in mlx4_dev_cap_dump()
1009 		 dev_cap->port_cap[1].max_port_width);  in mlx4_dev_cap_dump()
1034 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)  in mlx4_QUERY_PORT()  argument
1056 		port_cap->max_vl	   = field >> 4;  in mlx4_QUERY_PORT()
1058 		port_cap->ib_mtu	   = field >> 4;  in mlx4_QUERY_PORT()
1059 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1061 		port_cap->max_gids	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1063 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1083 		port_cap->supported_port_types = field & 3;  in mlx4_QUERY_PORT()
1084 		port_cap->suggested_type = (field >> 3) & 1;  in mlx4_QUERY_PORT()
1085 		port_cap->default_sense = (field >> 4) & 1;  in mlx4_QUERY_PORT()
1086 		port_cap->dmfs_optimized_state = (field >> 5) & 1;  in mlx4_QUERY_PORT()
1088 		port_cap->ib_mtu	   = field & 0xf;  in mlx4_QUERY_PORT()
1090 		port_cap->max_port_width = field & 0xf;  in mlx4_QUERY_PORT()
1092 		port_cap->max_gids	   = 1 << (field >> 4);  in mlx4_QUERY_PORT()
1093 		port_cap->max_pkeys	   = 1 << (field & 0xf);  in mlx4_QUERY_PORT()
1095 		port_cap->max_vl	   = field & 0xf;  in mlx4_QUERY_PORT()
1097 		port_cap->log_max_macs  = field & 0xf;  in mlx4_QUERY_PORT()
1098 		port_cap->log_max_vlans = field >> 4;  in mlx4_QUERY_PORT()
1099 		MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);  in mlx4_QUERY_PORT()
1100 		MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);  in mlx4_QUERY_PORT()
1102 		port_cap->trans_type = field32 >> 24;  in mlx4_QUERY_PORT()
1103 		port_cap->vendor_oui = field32 & 0xffffff;  in mlx4_QUERY_PORT()
1104 		MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);  in mlx4_QUERY_PORT()
1105 		MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);  in mlx4_QUERY_PORT()