Lines Matching refs:param
1654 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) in mlx4_INIT_HCA() argument
1788 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); in mlx4_INIT_HCA()
1789 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); in mlx4_INIT_HCA()
1790 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); in mlx4_INIT_HCA()
1791 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); in mlx4_INIT_HCA()
1792 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); in mlx4_INIT_HCA()
1793 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); in mlx4_INIT_HCA()
1794 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); in mlx4_INIT_HCA()
1795 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); in mlx4_INIT_HCA()
1796 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); in mlx4_INIT_HCA()
1797 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); in mlx4_INIT_HCA()
1798 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); in mlx4_INIT_HCA()
1799 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); in mlx4_INIT_HCA()
1800 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); in mlx4_INIT_HCA()
1809 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); in mlx4_INIT_HCA()
1810 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1812 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1839 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); in mlx4_INIT_HCA()
1840 MLX4_PUT(inbox, param->log_mc_entry_sz, in mlx4_INIT_HCA()
1842 MLX4_PUT(inbox, param->log_mc_hash_sz, in mlx4_INIT_HCA()
1844 MLX4_PUT(inbox, param->log_mc_table_sz, in mlx4_INIT_HCA()
1853 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1854 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); in mlx4_INIT_HCA()
1855 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); in mlx4_INIT_HCA()
1856 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); in mlx4_INIT_HCA()
1857 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); in mlx4_INIT_HCA()
1861 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); in mlx4_INIT_HCA()
1862 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); in mlx4_INIT_HCA()
1881 struct mlx4_init_hca_param *param) in mlx4_QUERY_HCA() argument
1910 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); in mlx4_QUERY_HCA()
1911 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); in mlx4_QUERY_HCA()
1915 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); in mlx4_QUERY_HCA()
1916 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); in mlx4_QUERY_HCA()
1917 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1918 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); in mlx4_QUERY_HCA()
1919 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1920 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); in mlx4_QUERY_HCA()
1921 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); in mlx4_QUERY_HCA()
1922 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); in mlx4_QUERY_HCA()
1923 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); in mlx4_QUERY_HCA()
1924 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); in mlx4_QUERY_HCA()
1925 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); in mlx4_QUERY_HCA()
1926 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); in mlx4_QUERY_HCA()
1927 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); in mlx4_QUERY_HCA()
1931 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; in mlx4_QUERY_HCA()
1935 param->steering_mode = MLX4_STEERING_MODE_B0; in mlx4_QUERY_HCA()
1937 param->steering_mode = MLX4_STEERING_MODE_A0; in mlx4_QUERY_HCA()
1941 param->rss_ip_frags = 1; in mlx4_QUERY_HCA()
1944 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_QUERY_HCA()
1945 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); in mlx4_QUERY_HCA()
1946 MLX4_GET(param->log_mc_entry_sz, outbox, in mlx4_QUERY_HCA()
1948 MLX4_GET(param->log_mc_table_sz, outbox, in mlx4_QUERY_HCA()
1952 param->dmfs_high_steer_mode = in mlx4_QUERY_HCA()
1955 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); in mlx4_QUERY_HCA()
1956 MLX4_GET(param->log_mc_entry_sz, outbox, in mlx4_QUERY_HCA()
1958 MLX4_GET(param->log_mc_hash_sz, outbox, in mlx4_QUERY_HCA()
1960 MLX4_GET(param->log_mc_table_sz, outbox, in mlx4_QUERY_HCA()
1967 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; in mlx4_QUERY_HCA()
1969 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; in mlx4_QUERY_HCA()
1974 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; in mlx4_QUERY_HCA()
1975 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; in mlx4_QUERY_HCA()
1976 param->cqe_size = 1 << ((byte_field & in mlx4_QUERY_HCA()
1978 param->eqe_size = 1 << (((byte_field & in mlx4_QUERY_HCA()
1984 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); in mlx4_QUERY_HCA()
1985 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); in mlx4_QUERY_HCA()
1986 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); in mlx4_QUERY_HCA()
1987 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); in mlx4_QUERY_HCA()
1988 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); in mlx4_QUERY_HCA()
1992 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); in mlx4_QUERY_HCA()
1993 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); in mlx4_QUERY_HCA()