Lines Matching refs:field
196 u8 field; in mlx4_QUERY_FUNC() local
222 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); in mlx4_QUERY_FUNC()
223 func->bus = field & 0xf; in mlx4_QUERY_FUNC()
224 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); in mlx4_QUERY_FUNC()
225 func->device = field & 0xf1; in mlx4_QUERY_FUNC()
226 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
227 func->function = field & 0x7; in mlx4_QUERY_FUNC()
228 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); in mlx4_QUERY_FUNC()
229 func->physical_function = field & 0xf; in mlx4_QUERY_FUNC()
234 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); in mlx4_QUERY_FUNC()
235 func->rsvd_uars = field & 0x0f; in mlx4_QUERY_FUNC()
253 u8 field, port; in mlx4_QUERY_FUNC_CAP_wrapper() local
322 field = vhcr->in_modifier - in mlx4_QUERY_FUNC_CAP_wrapper()
324 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
330 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; in mlx4_QUERY_FUNC_CAP_wrapper()
334 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; in mlx4_QUERY_FUNC_CAP_wrapper()
338 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
360 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | in mlx4_QUERY_FUNC_CAP_wrapper()
363 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
365 field = min( in mlx4_QUERY_FUNC_CAP_wrapper()
368 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
373 field = 0; /* protected FMR support not available as yet */ in mlx4_QUERY_FUNC_CAP_wrapper()
374 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); in mlx4_QUERY_FUNC_CAP_wrapper()
441 u8 field, op_modifier; in mlx4_QUERY_FUNC_CAP() local
463 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); in mlx4_QUERY_FUNC_CAP()
464 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { in mlx4_QUERY_FUNC_CAP()
469 func_cap->flags = field; in mlx4_QUERY_FUNC_CAP()
472 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); in mlx4_QUERY_FUNC_CAP()
473 func_cap->num_ports = field; in mlx4_QUERY_FUNC_CAP()
565 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); in mlx4_QUERY_FUNC_CAP()
566 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { in mlx4_QUERY_FUNC_CAP()
573 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); in mlx4_QUERY_FUNC_CAP()
574 func_cap->physical_port = field; in mlx4_QUERY_FUNC_CAP()
620 u8 field; in mlx4_QUERY_DEV_CAP() local
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
728 dev_cap->reserved_qps = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
730 dev_cap->max_qps = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
732 dev_cap->reserved_srqs = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
734 dev_cap->max_srqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
736 dev_cap->max_cq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
738 dev_cap->reserved_cqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
739 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); in mlx4_QUERY_DEV_CAP()
740 dev_cap->max_cqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
741 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); in mlx4_QUERY_DEV_CAP()
742 dev_cap->max_mpts = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
743 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
744 dev_cap->reserved_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
745 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); in mlx4_QUERY_DEV_CAP()
746 dev_cap->max_eqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
747 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); in mlx4_QUERY_DEV_CAP()
748 dev_cap->reserved_mtts = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
750 dev_cap->max_mrw_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); in mlx4_QUERY_DEV_CAP()
752 dev_cap->reserved_mrws = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); in mlx4_QUERY_DEV_CAP()
754 dev_cap->max_mtt_seg = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
758 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
760 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); in mlx4_QUERY_DEV_CAP()
762 field &= 0x1f; in mlx4_QUERY_DEV_CAP()
763 if (!field) in mlx4_QUERY_DEV_CAP()
766 dev_cap->max_gso_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
768 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); in mlx4_QUERY_DEV_CAP()
769 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
771 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
773 field &= 0xf; in mlx4_QUERY_DEV_CAP()
774 if (field) { in mlx4_QUERY_DEV_CAP()
776 dev_cap->max_rss_tbl_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); in mlx4_QUERY_DEV_CAP()
780 dev_cap->max_rdma_global = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); in mlx4_QUERY_DEV_CAP()
782 dev_cap->local_ca_ack_delay = field & 0x1f; in mlx4_QUERY_DEV_CAP()
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP()
784 dev_cap->num_ports = field & 0xf; in mlx4_QUERY_DEV_CAP()
785 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
786 dev_cap->max_msg_sz = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
787 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); in mlx4_QUERY_DEV_CAP()
788 if (field & 0x10) in mlx4_QUERY_DEV_CAP()
790 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); in mlx4_QUERY_DEV_CAP()
791 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
793 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; in mlx4_QUERY_DEV_CAP()
794 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP()
795 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
797 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP()
798 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
800 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); in mlx4_QUERY_DEV_CAP()
801 dev_cap->fs_max_num_qp_per_entry = field; in mlx4_QUERY_DEV_CAP()
802 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP()
803 if (field & 0x1) in mlx4_QUERY_DEV_CAP()
807 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP()
808 if (field & 0x80) in mlx4_QUERY_DEV_CAP()
813 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); in mlx4_QUERY_DEV_CAP()
814 dev_cap->reserved_uars = field >> 4; in mlx4_QUERY_DEV_CAP()
815 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
816 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); in mlx4_QUERY_DEV_CAP()
817 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
818 dev_cap->min_page_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
820 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP()
821 if (field & 0x80) { in mlx4_QUERY_DEV_CAP()
822 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
823 dev_cap->bf_reg_size = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
824 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); in mlx4_QUERY_DEV_CAP()
825 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) in mlx4_QUERY_DEV_CAP()
826 field = 3; in mlx4_QUERY_DEV_CAP()
827 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
832 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); in mlx4_QUERY_DEV_CAP()
833 dev_cap->max_sq_sg = field; in mlx4_QUERY_DEV_CAP()
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
838 dev_cap->max_qp_per_mcg = 1 << field; in mlx4_QUERY_DEV_CAP()
839 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
840 dev_cap->reserved_mgms = field & 0xf; in mlx4_QUERY_DEV_CAP()
841 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); in mlx4_QUERY_DEV_CAP()
842 dev_cap->max_mcgs = 1 << field; in mlx4_QUERY_DEV_CAP()
843 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
844 dev_cap->reserved_pds = field >> 4; in mlx4_QUERY_DEV_CAP()
845 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); in mlx4_QUERY_DEV_CAP()
846 dev_cap->max_pds = 1 << (field & 0x3f); in mlx4_QUERY_DEV_CAP()
847 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
848 dev_cap->reserved_xrcds = field >> 4; in mlx4_QUERY_DEV_CAP()
849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); in mlx4_QUERY_DEV_CAP()
850 dev_cap->max_xrcds = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
874 dev_cap->max_srq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
875 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); in mlx4_QUERY_DEV_CAP()
876 dev_cap->max_qp_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
877 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); in mlx4_QUERY_DEV_CAP()
878 dev_cap->resize_srq = field & 1; in mlx4_QUERY_DEV_CAP()
879 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); in mlx4_QUERY_DEV_CAP()
880 dev_cap->max_rq_sg = field; in mlx4_QUERY_DEV_CAP()
883 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP()
884 if (field & (1 << 4)) in mlx4_QUERY_DEV_CAP()
886 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
888 if (field & (1 << 6)) in mlx4_QUERY_DEV_CAP()
890 if (field & (1 << 7)) in mlx4_QUERY_DEV_CAP()
896 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP()
897 if (field & 0x20) in mlx4_QUERY_DEV_CAP()
899 if (field & (1 << 2)) in mlx4_QUERY_DEV_CAP()
908 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); in mlx4_QUERY_DEV_CAP()
909 if (field & 1<<6) in mlx4_QUERY_DEV_CAP()
911 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP()
912 if (field & 1<<3) in mlx4_QUERY_DEV_CAP()
914 if (field & (1 << 5)) in mlx4_QUERY_DEV_CAP()
1038 u8 field; in mlx4_QUERY_PORT() local
1055 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_PORT()
1056 port_cap->max_vl = field >> 4; in mlx4_QUERY_PORT()
1057 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1058 port_cap->ib_mtu = field >> 4; in mlx4_QUERY_PORT()
1059 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1060 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); in mlx4_QUERY_PORT()
1061 port_cap->max_gids = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1062 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); in mlx4_QUERY_PORT()
1063 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1082 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); in mlx4_QUERY_PORT()
1083 port_cap->supported_port_types = field & 3; in mlx4_QUERY_PORT()
1084 port_cap->suggested_type = (field >> 3) & 1; in mlx4_QUERY_PORT()
1085 port_cap->default_sense = (field >> 4) & 1; in mlx4_QUERY_PORT()
1086 port_cap->dmfs_optimized_state = (field >> 5) & 1; in mlx4_QUERY_PORT()
1087 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); in mlx4_QUERY_PORT()
1088 port_cap->ib_mtu = field & 0xf; in mlx4_QUERY_PORT()
1089 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); in mlx4_QUERY_PORT()
1090 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1091 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); in mlx4_QUERY_PORT()
1092 port_cap->max_gids = 1 << (field >> 4); in mlx4_QUERY_PORT()
1093 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1094 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); in mlx4_QUERY_PORT()
1095 port_cap->max_vl = field & 0xf; in mlx4_QUERY_PORT()
1096 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); in mlx4_QUERY_PORT()
1097 port_cap->log_max_macs = field & 0xf; in mlx4_QUERY_PORT()
1098 port_cap->log_max_vlans = field >> 4; in mlx4_QUERY_PORT()
1126 u8 field; in mlx4_QUERY_DEV_CAP_wrapper() local
1163 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1164 field &= ~0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1165 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1166 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1169 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1170 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1171 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1174 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1175 field &= 0xd7; in mlx4_QUERY_DEV_CAP_wrapper()
1176 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); in mlx4_QUERY_DEV_CAP_wrapper()
1179 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1180 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1181 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1184 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1185 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1186 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1196 MLX4_GET(field, outbox->buf, in mlx4_QUERY_DEV_CAP_wrapper()
1198 field &= 0x7f; in mlx4_QUERY_DEV_CAP_wrapper()
1199 MLX4_PUT(outbox->buf, field, in mlx4_QUERY_DEV_CAP_wrapper()
1204 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1205 field &= ~0x80; in mlx4_QUERY_DEV_CAP_wrapper()
1206 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1215 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1216 field &= 0xfe; in mlx4_QUERY_DEV_CAP_wrapper()
1217 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1224 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1225 field &= 0xef; in mlx4_QUERY_DEV_CAP_wrapper()
1226 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); in mlx4_QUERY_DEV_CAP_wrapper()
1229 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1230 field &= 0xfb; in mlx4_QUERY_DEV_CAP_wrapper()
1231 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); in mlx4_QUERY_DEV_CAP_wrapper()
1313 u16 field; in mlx4_get_slave_pkey_gid_tbl_len() local
1328 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1329 *gid_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
1331 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); in mlx4_get_slave_pkey_gid_tbl_len()
1332 *pkey_tbl_len = field; in mlx4_get_slave_pkey_gid_tbl_len()
2093 u16 field; in mlx4_INIT_PORT() local
2120 field = 128 << dev->caps.ib_mtu_cap[port]; in mlx4_INIT_PORT()
2121 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); in mlx4_INIT_PORT()
2122 field = dev->caps.gid_table_len[port]; in mlx4_INIT_PORT()
2123 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); in mlx4_INIT_PORT()
2124 field = dev->caps.pkey_table_len[port]; in mlx4_INIT_PORT()
2125 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); in mlx4_INIT_PORT()