Lines Matching refs:caps
323 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
351 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], in mlx4_QUERY_FUNC_CAP_wrapper()
366 bitmap_weight(actv_ports.ports, dev->caps.num_ports), in mlx4_QUERY_FUNC_CAP_wrapper()
367 dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
370 size = dev->caps.function_caps; /* set PF behaviours */ in mlx4_QUERY_FUNC_CAP_wrapper()
378 size = dev->caps.num_qps; in mlx4_QUERY_FUNC_CAP_wrapper()
383 size = dev->caps.num_srqs; in mlx4_QUERY_FUNC_CAP_wrapper()
388 size = dev->caps.num_cqs; in mlx4_QUERY_FUNC_CAP_wrapper()
391 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || in mlx4_QUERY_FUNC_CAP_wrapper()
395 dev->caps.num_eqs : in mlx4_QUERY_FUNC_CAP_wrapper()
396 rounddown_pow_of_two(dev->caps.num_eqs); in mlx4_QUERY_FUNC_CAP_wrapper()
398 size = dev->caps.reserved_eqs; in mlx4_QUERY_FUNC_CAP_wrapper()
412 size = dev->caps.num_mpts; in mlx4_QUERY_FUNC_CAP_wrapper()
417 size = dev->caps.num_mtts; in mlx4_QUERY_FUNC_CAP_wrapper()
420 size = dev->caps.num_mgms + dev->caps.num_amgms; in mlx4_QUERY_FUNC_CAP_wrapper()
428 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); in mlx4_QUERY_FUNC_CAP_wrapper()
546 if (gen_or_port > dev->caps.num_ports) { in mlx4_QUERY_FUNC_CAP()
552 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { in mlx4_QUERY_FUNC_CAP()
564 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { in mlx4_QUERY_FUNC_CAP()
1146 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_DEV_CAP_wrapper()
1149 bitmap_weight(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_DEV_CAP_wrapper()
1156 for (; slave_port < dev->caps.num_ports; ++slave_port) in mlx4_QUERY_DEV_CAP_wrapper()
1165 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; in mlx4_QUERY_DEV_CAP_wrapper()
1195 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_QUERY_DEV_CAP_wrapper()
1271 if (!err && dev->caps.function != slave) { in mlx4_QUERY_PORT_wrapper()
1282 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); in mlx4_QUERY_PORT_wrapper()
1293 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) in mlx4_QUERY_PORT_wrapper()
1300 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; in mlx4_QUERY_PORT_wrapper()
1484 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | in mlx4_QUERY_FW()
1489 dev->caps.function = lg; in mlx4_QUERY_FW()
1501 (int) (dev->caps.fw_ver >> 32), in mlx4_QUERY_FW()
1502 (int) (dev->caps.fw_ver >> 16) & 0xffff, in mlx4_QUERY_FW()
1503 (int) dev->caps.fw_ver & 0xffff); in mlx4_QUERY_FW()
1517 (int) (dev->caps.fw_ver >> 32), in mlx4_QUERY_FW()
1518 (int) (dev->caps.fw_ver >> 16) & 0xffff, in mlx4_QUERY_FW()
1519 (int) dev->caps.fw_ver & 0xffff, in mlx4_QUERY_FW()
1736 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) in mlx4_INIT_HCA()
1740 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) in mlx4_INIT_HCA()
1744 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) in mlx4_INIT_HCA()
1748 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) in mlx4_INIT_HCA()
1752 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { in mlx4_INIT_HCA()
1754 dev->caps.eqe_size = 64; in mlx4_INIT_HCA()
1755 dev->caps.eqe_factor = 1; in mlx4_INIT_HCA()
1757 dev->caps.eqe_size = 32; in mlx4_INIT_HCA()
1758 dev->caps.eqe_factor = 0; in mlx4_INIT_HCA()
1761 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { in mlx4_INIT_HCA()
1763 dev->caps.cqe_size = 64; in mlx4_INIT_HCA()
1764 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_INIT_HCA()
1766 dev->caps.cqe_size = 32; in mlx4_INIT_HCA()
1770 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && in mlx4_INIT_HCA()
1771 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { in mlx4_INIT_HCA()
1772 dev->caps.eqe_size = cache_line_size(); in mlx4_INIT_HCA()
1773 dev->caps.cqe_size = cache_line_size(); in mlx4_INIT_HCA()
1774 dev->caps.eqe_factor = 0; in mlx4_INIT_HCA()
1775 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | in mlx4_INIT_HCA()
1776 (ilog2(dev->caps.eqe_size) - 5)), in mlx4_INIT_HCA()
1780 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_INIT_HCA()
1783 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) in mlx4_INIT_HCA()
1803 if (dev->caps.steering_mode == in mlx4_INIT_HCA()
1817 if (dev->caps.dmfs_high_steer_mode != in mlx4_INIT_HCA()
1832 if (dev->caps.dmfs_high_steer_mode != in mlx4_INIT_HCA()
1835 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] in mlx4_INIT_HCA()
1846 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) in mlx4_INIT_HCA()
1865 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { in mlx4_INIT_HCA()
2023 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); in mlx4_hca_core_clock_update()
2060 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { in mlx4_INIT_PORT_wrapper()
2116 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; in mlx4_INIT_PORT()
2117 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; in mlx4_INIT_PORT()
2120 field = 128 << dev->caps.ib_mtu_cap[port]; in mlx4_INIT_PORT()
2122 field = dev->caps.gid_table_len[port]; in mlx4_INIT_PORT()
2124 field = dev->caps.pkey_table_len[port]; in mlx4_INIT_PORT()
2159 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { in mlx4_CLOSE_PORT_wrapper()
2277 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) in mlx4_config_dev_retrieval()
2398 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_get_phys_port_id()
2410 dev->caps.phys_port_id[port] = (u64)guid_lo | in mlx4_get_phys_port_id()
2490 if (dev->caps.steering_mode == in mlx4_opreq_action()
2586 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) in mlx4_config_mad_demux()