Lines Matching refs:mfunc
256 u32 status = readl(&priv->mfunc.comm->slave_read); in comm_pending()
281 &priv->mfunc.comm->slave_write); in mlx4_comm_cmd_post()
521 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; in mlx4_slave_cmd()
941 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; in mlx4_MAD_IFC_wrapper()
1650 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; in mlx4_master_process_vhcr()
1667 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1668 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1796 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1797 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1805 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) in mlx4_master_process_vhcr()
1827 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1828 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1836 if (!(priv->mfunc.master.slave_state[slave].active && in mlx4_master_immediate_activate_vlan_qos()
1905 queue_work(priv->mfunc.master.comm_wq, &work->work); in mlx4_master_immediate_activate_vlan_qos()
1915 port_qos_ctl = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_default_port_qos()
1938 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_allocate_port_vpps()
1983 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_activate_admin_state()
1984 priv->mfunc.master.vf_admin[slave].enable_smi[port]; in mlx4_master_activate_admin_state()
1985 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_activate_admin_state()
1986 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_activate_admin_state()
2036 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_deactivate_admin_state()
2038 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_deactivate_admin_state()
2056 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; in mlx4_master_do_cmd()
2103 priv->mfunc.master.slave_state[slave].cookie = 0; in mlx4_master_do_cmd()
2145 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2150 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2157 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2176 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2179 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2185 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2196 struct mlx4_mfunc *mfunc = in mlx4_master_comm_channel() local
2199 container_of(mfunc, struct mlx4_priv, mfunc); in mlx4_master_comm_channel()
2219 &mfunc->comm[slave].slave_write)); in mlx4_master_comm_channel()
2220 slt = swab32(readl(&mfunc->comm[slave].slave_read)) in mlx4_master_comm_channel()
2255 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)); in sync_toggles()
2262 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)); in sync_toggles()
2266 wr_toggle = swab32(readl(&priv->mfunc.comm-> in sync_toggles()
2286 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read); in sync_toggles()
2287 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write); in sync_toggles()
2300 priv->mfunc.comm = in mlx4_multi_func_init()
2305 priv->mfunc.comm = in mlx4_multi_func_init()
2308 if (!priv->mfunc.comm) { in mlx4_multi_func_init()
2317 priv->mfunc.master.slave_state = in mlx4_multi_func_init()
2320 if (!priv->mfunc.master.slave_state) in mlx4_multi_func_init()
2323 priv->mfunc.master.vf_admin = in mlx4_multi_func_init()
2326 if (!priv->mfunc.master.vf_admin) in mlx4_multi_func_init()
2329 priv->mfunc.master.vf_oper = in mlx4_multi_func_init()
2332 if (!priv->mfunc.master.vf_oper) in mlx4_multi_func_init()
2336 vf_admin = &priv->mfunc.master.vf_admin[i]; in mlx4_multi_func_init()
2337 vf_oper = &priv->mfunc.master.vf_oper[i]; in mlx4_multi_func_init()
2338 s_state = &priv->mfunc.master.slave_state[i]; in mlx4_multi_func_init()
2340 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]); in mlx4_multi_func_init()
2344 &priv->mfunc.comm[i].slave_write); in mlx4_multi_func_init()
2346 &priv->mfunc.comm[i].slave_read); in mlx4_multi_func_init()
2385 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe)); in mlx4_multi_func_init()
2386 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD; in mlx4_multi_func_init()
2387 INIT_WORK(&priv->mfunc.master.comm_work, in mlx4_multi_func_init()
2389 INIT_WORK(&priv->mfunc.master.slave_event_work, in mlx4_multi_func_init()
2391 INIT_WORK(&priv->mfunc.master.slave_flr_event_work, in mlx4_multi_func_init()
2393 spin_lock_init(&priv->mfunc.master.slave_state_lock); in mlx4_multi_func_init()
2394 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock); in mlx4_multi_func_init()
2395 priv->mfunc.master.comm_wq = in mlx4_multi_func_init()
2397 if (!priv->mfunc.master.comm_wq) in mlx4_multi_func_init()
2413 flush_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_init()
2414 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_init()
2418 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_init()
2420 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_init()
2422 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_init()
2424 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_init()
2426 iounmap(priv->mfunc.comm); in mlx4_multi_func_init()
2429 priv->mfunc.vhcr, in mlx4_multi_func_init()
2430 priv->mfunc.vhcr_dma); in mlx4_multi_func_init()
2431 priv->mfunc.vhcr = NULL; in mlx4_multi_func_init()
2459 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) { in mlx4_cmd_init()
2460 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev, in mlx4_cmd_init()
2462 &priv->mfunc.vhcr_dma, in mlx4_cmd_init()
2464 if (!priv->mfunc.vhcr) in mlx4_cmd_init()
2498 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read)); in mlx4_report_internal_err_comm_event()
2501 &priv->mfunc.comm[slave].slave_read); in mlx4_report_internal_err_comm_event()
2515 flush_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_cleanup()
2516 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_cleanup()
2519 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_cleanup()
2521 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_cleanup()
2522 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_cleanup()
2523 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_cleanup()
2527 iounmap(priv->mfunc.comm); in mlx4_multi_func_cleanup()
2544 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr && in mlx4_cmd_cleanup()
2547 priv->mfunc.vhcr, priv->mfunc.vhcr_dma); in mlx4_cmd_cleanup()
2548 priv->mfunc.vhcr = NULL; in mlx4_cmd_cleanup()
2814 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_vport_qos()
2861 info = &priv->mfunc.master.qos_ctl[port]; in mlx4_is_vf_vst_and_prio_qos()
2916 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_mac()
2943 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_vlan()
2991 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_rate()
3024 if (priv->mfunc.master.slave_state[slave].active && in mlx4_set_vf_rate()
3044 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_get_slave_default_vlan()
3072 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_spoofchk()
3092 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_get_vf_config()
3153 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_link_state()
3175 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] == in mlx4_vf_smi_enabled()
3191 return priv->mfunc.master.vf_admin[slave].enable_smi[port] == in mlx4_vf_get_enable_smi_admin()
3209 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled; in mlx4_vf_set_enable_smi_admin()