58 		hw->aq.arq.tail = I40E_VF_ARQT1;  in i40e_adminq_init_regs()
59 		hw->aq.arq.head = I40E_VF_ARQH1;  in i40e_adminq_init_regs()
60 		hw->aq.arq.len  = I40E_VF_ARQLEN1;  in i40e_adminq_init_regs()
61 		hw->aq.arq.bal  = I40E_VF_ARQBAL1;  in i40e_adminq_init_regs()
62 		hw->aq.arq.bah  = I40E_VF_ARQBAH1;  in i40e_adminq_init_regs()
69 		hw->aq.arq.tail = I40E_PF_ARQT;  in i40e_adminq_init_regs()
70 		hw->aq.arq.head = I40E_PF_ARQH;  in i40e_adminq_init_regs()
71 		hw->aq.arq.len  = I40E_PF_ARQLEN;  in i40e_adminq_init_regs()
72 		hw->aq.arq.bal  = I40E_PF_ARQBAL;  in i40e_adminq_init_regs()
73 		hw->aq.arq.bah  = I40E_PF_ARQBAH;  in i40e_adminq_init_regs()
112 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,  in i40e_alloc_adminq_arq_ring()
142 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);  in i40e_free_adminq_arq()
161 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,  in i40e_alloc_arq_bufs()
165 	hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;  in i40e_alloc_arq_bufs()
169 		bi = &hw->aq.arq.r.arq_bi[i];  in i40e_alloc_arq_bufs()
178 		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);  in i40e_alloc_arq_bufs()
206 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);  in i40e_alloc_arq_bufs()
207 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);  in i40e_alloc_arq_bufs()
262 		i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);  in i40e_free_arq_bufs()
265 	i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);  in i40e_free_arq_bufs()
268 	i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);  in i40e_free_arq_bufs()
335 	wr32(hw, hw->aq.arq.head, 0);  in i40e_config_arq_regs()
336 	wr32(hw, hw->aq.arq.tail, 0);  in i40e_config_arq_regs()
339 	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |  in i40e_config_arq_regs()
341 	wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));  in i40e_config_arq_regs()
342 	wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));  in i40e_config_arq_regs()
345 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);  in i40e_config_arq_regs()
348 	reg = rd32(hw, hw->aq.arq.bal);  in i40e_config_arq_regs()
349 	if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))  in i40e_config_arq_regs()
431 	if (hw->aq.arq.count > 0) {  in i40e_init_arq()
444 	hw->aq.arq.next_to_use = 0;  in i40e_init_arq()
445 	hw->aq.arq.next_to_clean = 0;  in i40e_init_arq()
446 	hw->aq.arq.count = hw->aq.num_arq_entries;  in i40e_init_arq()
516 	if (hw->aq.arq.count == 0)  in i40e_shutdown_arq()
520 	wr32(hw, hw->aq.arq.head, 0);  in i40e_shutdown_arq()
521 	wr32(hw, hw->aq.arq.tail, 0);  in i40e_shutdown_arq()
522 	wr32(hw, hw->aq.arq.len, 0);  in i40e_shutdown_arq()
523 	wr32(hw, hw->aq.arq.bal, 0);  in i40e_shutdown_arq()
524 	wr32(hw, hw->aq.arq.bah, 0);  in i40e_shutdown_arq()
529 	hw->aq.arq.count = 0; /* to indicate uninitialized queue */  in i40e_shutdown_arq()
890 	u16 ntc = hw->aq.arq.next_to_clean;  in i40evf_clean_arq_element()
902 	ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);  in i40evf_clean_arq_element()
910 	desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);  in i40evf_clean_arq_element()
928 		memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,  in i40evf_clean_arq_element()
939 	bi = &hw->aq.arq.r.arq_bi[ntc];  in i40evf_clean_arq_element()
950 	wr32(hw, hw->aq.arq.tail, ntc);  in i40evf_clean_arq_element()
955 	hw->aq.arq.next_to_clean = ntc;  in i40evf_clean_arq_element()
956 	hw->aq.arq.next_to_use = ntu;  in i40evf_clean_arq_element()
961 		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);  in i40evf_clean_arq_element()
975 	hw->aq.arq.next_to_use = 0;  in i40evf_resume_aq()
976 	hw->aq.arq.next_to_clean = 0;  in i40evf_resume_aq()