Lines Matching refs:u32
592 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
593 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
594 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
595 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
596 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
597 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
598 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
599 u32 rbyt; /* 0x.69c - Receive Byte Counter */
600 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
601 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
602 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
603 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
604 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
605 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
606 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
607 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
608 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
609 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
610 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
611 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
612 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
613 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
614 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
615 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
616 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
617 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
618 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
619 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
620 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
621 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
622 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
623 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
624 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
625 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
626 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
627 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
629 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
630 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
631 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
632 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
633 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
634 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
635 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
636 u32 car1; /* 0x.730 - Carry Register One */
637 u32 car2; /* 0x.734 - Carry Register Two */
638 u32 cam1; /* 0x.738 - Carry Mask Register One */
639 u32 cam2; /* 0x.73c - Carry Mask Register Two */
658 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
666 u32 tsec_id; /* 0x.000 - Controller ID register */
667 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
669 u32 ievent; /* 0x.010 - Interrupt Event Register */
670 u32 imask; /* 0x.014 - Interrupt Mask Register */
671 u32 edis; /* 0x.018 - Error Disabled Register */
672 u32 emapg; /* 0x.01c - Group Error mapping register */
673 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
674 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
675 u32 ptv; /* 0x.028 - Pause Time Value Register */
676 u32 dmactrl; /* 0x.02c - DMA Control Register */
677 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
679 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
681 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
683 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
685 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
688 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
690 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
691 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
693 u32 tctrl; /* 0x.100 - Transmit Control Register */
694 u32 tstat; /* 0x.104 - Transmit Status Register */
695 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
696 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
697 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
698 u32 tqueue; /* 0x.114 - Transmit queue control register */
700 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
701 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
703 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
705 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
707 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
709 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
711 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
713 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
715 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
717 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
719 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
721 u32 tbaseh; /* 0x.200 - TxBD base address high */
722 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
724 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
726 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
728 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
730 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
732 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
734 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
736 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
738 u32 rctrl; /* 0x.300 - Receive Control Register */
739 u32 rstat; /* 0x.304 - Receive Status Register */
741 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
742 u32 rqueue; /* 0x.314 - Receive queue control register */
743 u32 rir0; /* 0x.318 - Ring mapping register 0 */
744 u32 rir1; /* 0x.31c - Ring mapping register 1 */
745 u32 rir2; /* 0x.320 - Ring mapping register 2 */
746 u32 rir3; /* 0x.324 - Ring mapping register 3 */
748 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
749 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
750 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
751 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
752 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
754 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
756 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
758 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
760 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
762 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
764 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
766 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
768 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
770 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
772 u32 rbaseh; /* 0x.400 - RxBD base address high */
773 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
775 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
777 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
779 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
781 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
783 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
785 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
787 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
789 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
790 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
791 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
792 u32 hafdup; /* 0x.50c - Half Duplex Register */
793 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
796 u32 ifctrl; /* 0x.538 - Interface control register */
797 u32 ifstat; /* 0x.53c - Interface Status Register */
798 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
799 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
800 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
801 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
802 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
803 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
804 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
805 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
806 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
807 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
808 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
809 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
810 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
811 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
812 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
813 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
814 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
815 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
816 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
817 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
818 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
819 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
820 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
821 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
822 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
823 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
824 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
825 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
826 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
827 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
828 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
829 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
832 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
834 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
835 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
836 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
837 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
838 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
839 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
840 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
841 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
843 u32 gaddr0; /* 0x.880 - Group address register 0 */
844 u32 gaddr1; /* 0x.884 - Group address register 1 */
845 u32 gaddr2; /* 0x.888 - Group address register 2 */
846 u32 gaddr3; /* 0x.88c - Group address register 3 */
847 u32 gaddr4; /* 0x.890 - Group address register 4 */
848 u32 gaddr5; /* 0x.894 - Group address register 5 */
849 u32 gaddr6; /* 0x.898 - Group address register 6 */
850 u32 gaddr7; /* 0x.89c - Group address register 7 */
852 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
855 u32 attr; /* 0x.bf8 - Attributes Register */
856 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
857 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
858 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
859 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
860 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
861 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
862 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
863 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
864 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
866 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
868 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
870 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
872 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
874 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
876 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
878 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
880 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
883 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
884 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
885 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
886 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
888 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
889 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
890 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
891 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
892 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
893 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
894 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
895 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
897 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
898 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
899 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
900 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
901 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
902 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
903 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
904 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
1042 u32 __iomem *rfbptr;
1116 u32 device_flags;
1173 u32 rqueue;
1174 u32 tqueue;
1180 u32 cur_filer_idx;
1187 u32 __iomem *hash_regs[16];
1202 static inline u32 gfar_read(unsigned __iomem *addr) in gfar_read()
1204 u32 val; in gfar_read()
1209 static inline void gfar_write(unsigned __iomem *addr, u32 val) in gfar_write()
1237 u32 __iomem *baddr = ®s->isrg0; in gfar_write_isrg()
1238 u32 isrg = 0; in gfar_write_isrg()
1292 u32 lstatus = be32_to_cpu(bdp->lstatus); in gfar_clear_txbd_status()
1306 u32 regnum, u32 read);
1329 u32 ctrl;
1330 u32 prop;
1336 u32 index;