67 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))  macro
73 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
76 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
87 	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);  in whack_reset()
231 	FW(fecp, grp_hash_table_high, fep->fec.hthi);  in set_multicast_finish()
232 	FW(fecp, grp_hash_table_low, fep->fec.htlo);  in set_multicast_finish()
272 	FW(fecp, addr_low, addrhi);  in restart()
273 	FW(fecp, addr_high, addrlo);  in restart()
278 	FW(fecp, grp_hash_table_high, fep->fec.hthi);  in restart()
279 	FW(fecp, grp_hash_table_low, fep->fec.htlo);  in restart()
284 	FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);  in restart()
286 	FW(fecp, r_cntrl, PKT_MAXBUF_SIZE << 16);  in restart()
288 	FW(fecp, r_hash, PKT_MAXBUF_SIZE);  in restart()
298 	FW(fecp, r_des_start, rx_bd_base_phys);  in restart()
299 	FW(fecp, x_des_start, tx_bd_base_phys);  in restart()
309 	FW(fecp, fun_code, 0x78000000);  in restart()
315 	FW(fecp, mii_speed, fec_inf->mii_speed);  in restart()
320 	FW(fecp, ievent, 0xffc0);  in restart()
322 	FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);  in restart()
324 	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);	/* MII enable */  in restart()
350 	FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |  in restart()
356 	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);  in restart()
357 	FW(fecp, r_des_active, 0x01000000);  in restart()
373 	FW(fecp, x_cntrl, 0x01);	/* Graceful transmit stop */  in stop()
383 	FW(fecp, imask, 0);  in stop()
394 		FW(fecp, ievent, FEC_ENET_MII);  in stop()
395 		FW(fecp, mii_speed, feci->mii_speed);  in stop()
404 	FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);  in napi_clear_rx_event()
428 	FW(fecp, ievent, FEC_NAPI_TX_EVENT_MSK);  in napi_clear_tx_event()
452 	FW(fecp, r_des_active, 0x01000000);  in rx_bd_done()
460 	FW(fecp, x_des_active, 0x01000000);  in tx_kickstart()
476 	FW(fecp, ievent, int_events);  in clear_int_events()