Lines Matching defs:dmfe_board_info

211 struct dmfe_board_info {  struct
212 	u32 chip_id;			/* Chip vendor/Device ID */
213 	u8 chip_revision;		/* Chip revision */
214 	struct net_device *next_dev;	/* next device */
215 	struct pci_dev *pdev;		/* PCI device */
216 	spinlock_t lock;
218 	void __iomem *ioaddr;		/* I/O base address */
219 	u32 cr0_data;
220 	u32 cr5_data;
221 	u32 cr6_data;
222 	u32 cr7_data;
223 	u32 cr15_data;
226 	dma_addr_t buf_pool_dma_ptr;	/* Tx buffer pool memory */
227 	dma_addr_t buf_pool_dma_start;	/* Tx buffer pool align dword */
228 	dma_addr_t desc_pool_dma_ptr;	/* descriptor pool memory */
229 	dma_addr_t first_tx_desc_dma;
230 	dma_addr_t first_rx_desc_dma;
233 	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
234 	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
235 	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
236 	struct tx_desc *first_tx_desc;
237 	struct tx_desc *tx_insert_ptr;
238 	struct tx_desc *tx_remove_ptr;
239 	struct rx_desc *first_rx_desc;
240 	struct rx_desc *rx_insert_ptr;
241 	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
242 	unsigned long tx_packet_cnt;	/* transmitted packet count */
243 	unsigned long tx_queue_cnt;	/* wait to send packet count */
244 	unsigned long rx_avail_cnt;	/* available rx descriptor count */
245 	unsigned long interval_rx_cnt;	/* rx packet count a callback time */
247 	u16 HPNA_command;		/* For HPNA register 16 */
248 	u16 HPNA_timer;			/* For HPNA remote device check */
249 	u16 dbug_cnt;
250 	u16 NIC_capability;		/* NIC media capability */
251 	u16 PHY_reg4;			/* Saved Phyxcer register 4 value */
253 	u8 HPNA_present;		/* 0:none, 1:DM9801, 2:DM9802 */
254 	u8 chip_type;			/* Keep DM9102A chip type */
255 	u8 media_mode;			/* user specify media mode */
256 	u8 op_mode;			/* real work media mode */
257 	u8 phy_addr;
258 	u8 wait_reset;			/* Hardware failed, need to reset */
259 	u8 dm910x_chk_mode;		/* Operating mode check */
260 	u8 first_in_callback;		/* Flag to record state */
261 	u8 wol_mode;			/* user WOL settings */
262 	struct timer_list timer;
265 	unsigned long tx_fifo_underrun;
266 	unsigned long tx_loss_carrier;
267 	unsigned long tx_no_carrier;
268 	unsigned long tx_late_collision;
269 	unsigned long tx_excessive_collision;
270 	unsigned long tx_jabber_timeout;
271 	unsigned long reset_count;
272 	unsigned long reset_cr8;
273 	unsigned long reset_fatal;
274 	unsigned long reset_TXtimeout;
277 	unsigned char srom[128];