Lines Matching refs:adapter
37 static void t3_port_intr_clear(struct adapter *adapter, int idx);
55 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, in t3_wait_op_done_val() argument
59 u32 val = t3_read_reg(adapter, reg); in t3_wait_op_done_val()
84 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, in t3_write_regs() argument
88 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
103 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, in t3_set_reg_field() argument
106 u32 v = t3_read_reg(adapter, addr) & ~mask; in t3_set_reg_field()
108 t3_write_reg(adapter, addr, v | val); in t3_set_reg_field()
109 t3_read_reg(adapter, addr); /* flush */ in t3_set_reg_field()
124 static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg, in t3_read_indirect()
152 struct adapter *adap = mc7->adapter; in t3_mc7_bd_read()
196 static void mi1_init(struct adapter *adap, const struct adapter_info *ai) in mi1_init()
213 struct adapter *adapter = pi->adapter; in t3_mi1_read() local
217 mutex_lock(&adapter->mdio_lock); in t3_mi1_read()
218 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_read()
219 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_read()
220 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); in t3_mi1_read()
221 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_read()
223 ret = t3_read_reg(adapter, A_MI1_DATA); in t3_mi1_read()
224 mutex_unlock(&adapter->mdio_lock); in t3_mi1_read()
232 struct adapter *adapter = pi->adapter; in t3_mi1_write() local
236 mutex_lock(&adapter->mdio_lock); in t3_mi1_write()
237 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_write()
238 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_write()
239 t3_write_reg(adapter, A_MI1_DATA, val); in t3_mi1_write()
240 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in t3_mi1_write()
241 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_write()
242 mutex_unlock(&adapter->mdio_lock); in t3_mi1_write()
256 static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr, in mi1_wr_addr() argument
261 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); in mi1_wr_addr()
262 t3_write_reg(adapter, A_MI1_ADDR, addr); in mi1_wr_addr()
263 t3_write_reg(adapter, A_MI1_DATA, reg_addr); in mi1_wr_addr()
264 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); in mi1_wr_addr()
265 return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_wr_addr()
276 struct adapter *adapter = pi->adapter; in mi1_ext_read() local
279 mutex_lock(&adapter->mdio_lock); in mi1_ext_read()
280 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); in mi1_ext_read()
282 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); in mi1_ext_read()
283 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_read()
286 ret = t3_read_reg(adapter, A_MI1_DATA); in mi1_ext_read()
288 mutex_unlock(&adapter->mdio_lock); in mi1_ext_read()
296 struct adapter *adapter = pi->adapter; in mi1_ext_write() local
299 mutex_lock(&adapter->mdio_lock); in mi1_ext_write()
300 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr); in mi1_ext_write()
302 t3_write_reg(adapter, A_MI1_DATA, val); in mi1_ext_write()
303 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in mi1_ext_write()
304 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_write()
307 mutex_unlock(&adapter->mdio_lock); in mi1_ext_write()
548 int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
613 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data) in t3_seeprom_read() argument
618 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_read()
623 pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr); in t3_seeprom_read()
626 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); in t3_seeprom_read()
630 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); in t3_seeprom_read()
633 pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v); in t3_seeprom_read()
647 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data) in t3_seeprom_write() argument
651 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_write()
656 pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA, in t3_seeprom_write()
658 pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR, in t3_seeprom_write()
662 pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); in t3_seeprom_write()
666 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr); in t3_seeprom_write()
679 int t3_seeprom_wp(struct adapter *adapter, int enable) in t3_seeprom_wp() argument
681 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); in t3_seeprom_wp()
691 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) in get_vpd_params() argument
700 ret = t3_seeprom_read(adapter, VPD_BASE, (__le32 *)&vpd); in get_vpd_params()
706 ret = t3_seeprom_read(adapter, addr + i, in get_vpd_params()
720 if (adapter->params.rev == 0 && !vpd.port0_data[0]) { in get_vpd_params()
721 p->port_type[0] = uses_xaui(adapter) ? 1 : 2; in get_vpd_params()
722 p->port_type[1] = uses_xaui(adapter) ? 6 : 2; in get_vpd_params()
766 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, in sf1_read() argument
773 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_read()
775 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
776 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_read()
778 *valp = t3_read_reg(adapter, A_SF_DATA); in sf1_read()
793 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, in sf1_write() argument
798 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_write()
800 t3_write_reg(adapter, A_SF_DATA, val); in sf1_write()
801 t3_write_reg(adapter, A_SF_OP, in sf1_write()
803 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_write()
814 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) in flash_wait_op() argument
820 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 || in flash_wait_op()
821 (ret = sf1_read(adapter, 1, 0, &status)) != 0) in flash_wait_op()
845 static int t3_read_flash(struct adapter *adapter, unsigned int addr, in t3_read_flash() argument
855 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 || in t3_read_flash()
856 (ret = sf1_read(adapter, 1, 1, data)) != 0) in t3_read_flash()
860 ret = sf1_read(adapter, 4, nwords > 1, data); in t3_read_flash()
879 static int t3_write_flash(struct adapter *adapter, unsigned int addr, in t3_write_flash() argument
891 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_write_flash()
892 (ret = sf1_write(adapter, 4, 1, val)) != 0) in t3_write_flash()
900 ret = sf1_write(adapter, c, c != left, val); in t3_write_flash()
904 if ((ret = flash_wait_op(adapter, 5, 1)) != 0) in t3_write_flash()
908 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); in t3_write_flash()
924 int t3_get_tp_version(struct adapter *adapter, u32 *vers) in t3_get_tp_version() argument
929 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0); in t3_get_tp_version()
930 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0, in t3_get_tp_version()
935 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); in t3_get_tp_version()
946 int t3_check_tpsram_version(struct adapter *adapter) in t3_check_tpsram_version() argument
952 if (adapter->params.rev == T3_REV_A) in t3_check_tpsram_version()
956 ret = t3_get_tp_version(adapter, &vers); in t3_check_tpsram_version()
966 CH_ERR(adapter, "found wrong TP version (%u.%u), " in t3_check_tpsram_version()
983 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram, in t3_check_tpsram() argument
994 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n", in t3_check_tpsram()
1014 int t3_get_fw_version(struct adapter *adapter, u32 *vers) in t3_get_fw_version() argument
1016 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); in t3_get_fw_version()
1026 int t3_check_fw_version(struct adapter *adapter) in t3_check_fw_version() argument
1032 ret = t3_get_fw_version(adapter, &vers); in t3_check_fw_version()
1044 CH_WARN(adapter, "found old FW minor version(%u.%u), " in t3_check_fw_version()
1048 CH_WARN(adapter, "found newer FW version(%u.%u), " in t3_check_fw_version()
1064 static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end) in t3_flash_erase_sectors() argument
1069 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_flash_erase_sectors()
1070 (ret = sf1_write(adapter, 4, 0, in t3_flash_erase_sectors()
1072 (ret = flash_wait_op(adapter, 5, 500)) != 0) in t3_flash_erase_sectors()
1090 int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size) in t3_load_fw() argument
1105 CH_ERR(adapter, "corrupted firmware image, checksum %u\n", in t3_load_fw()
1110 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector); in t3_load_fw()
1118 ret = t3_write_flash(adapter, addr, chunk_size, fw_data); in t3_load_fw()
1127 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data); in t3_load_fw()
1130 CH_ERR(adapter, "firmware download failed, error %d\n", ret); in t3_load_fw()
1146 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, in t3_cim_ctl_blk_read()
1171 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG); in t3_gate_rx_traffic()
1172 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, in t3_gate_rx_traffic()
1176 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH); in t3_gate_rx_traffic()
1177 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0); in t3_gate_rx_traffic()
1179 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW); in t3_gate_rx_traffic()
1180 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0); in t3_gate_rx_traffic()
1190 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG, in t3_open_rx_traffic()
1193 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high); in t3_open_rx_traffic()
1194 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low); in t3_open_rx_traffic()
1206 void t3_link_changed(struct adapter *adapter, int port_id) in t3_link_changed() argument
1209 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_link_changed()
1220 t3_xgm_intr_enable(adapter, port_id); in t3_link_changed()
1222 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_changed()
1225 status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_link_changed()
1242 if (link_ok != lc->link_ok && adapter->params.rev > 0 && in t3_link_changed()
1243 uses_xaui(adapter)) { in t3_link_changed()
1246 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_changed()
1259 t3_os_link_changed(adapter, port_id, link_ok && !pi->link_fault, in t3_link_changed()
1263 void t3_link_fault(struct adapter *adapter, int port_id) in t3_link_fault() argument
1265 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_link_fault()
1274 if (adapter->params.rev > 0 && uses_xaui(adapter)) in t3_link_fault()
1275 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0); in t3_link_fault()
1277 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_fault()
1282 link_fault = t3_read_reg(adapter, in t3_link_fault()
1298 t3_os_link_fault(adapter, port_id, 0); in t3_link_fault()
1305 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_fault()
1312 t3_os_link_fault(adapter, port_id, link_ok); in t3_link_fault()
1369 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on) in t3_set_vlan_accel() argument
1371 t3_set_reg_field(adapter, A_TP_OUT_CONFIG, in t3_set_vlan_accel()
1398 static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, in t3_handle_intr_status() argument
1404 unsigned int status = t3_read_reg(adapter, reg) & mask; in t3_handle_intr_status()
1411 CH_ALERT(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1415 CH_WARN(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1421 t3_write_reg(adapter, reg, status); in t3_handle_intr_status()
1486 static void pci_intr_handler(struct adapter *adapter) in pci_intr_handler() argument
1514 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK, in pci_intr_handler()
1515 pcix1_intr_info, adapter->irq_stats)) in pci_intr_handler()
1516 t3_fatal_err(adapter); in pci_intr_handler()
1522 static void pcie_intr_handler(struct adapter *adapter) in pcie_intr_handler() argument
1544 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) in pcie_intr_handler()
1545 CH_ALERT(adapter, "PEX error code 0x%x\n", in pcie_intr_handler()
1546 t3_read_reg(adapter, A_PCIE_PEX_ERR)); in pcie_intr_handler()
1548 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, in pcie_intr_handler()
1549 pcie_intr_info, adapter->irq_stats)) in pcie_intr_handler()
1550 t3_fatal_err(adapter); in pcie_intr_handler()
1556 static void tp_intr_handler(struct adapter *adapter) in tp_intr_handler() argument
1572 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, in tp_intr_handler()
1573 adapter->params.rev < T3_REV_C ? in tp_intr_handler()
1575 t3_fatal_err(adapter); in tp_intr_handler()
1581 static void cim_intr_handler(struct adapter *adapter) in cim_intr_handler() argument
1611 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff, in cim_intr_handler()
1613 t3_fatal_err(adapter); in cim_intr_handler()
1619 static void ulprx_intr_handler(struct adapter *adapter) in ulprx_intr_handler() argument
1633 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff, in ulprx_intr_handler()
1635 t3_fatal_err(adapter); in ulprx_intr_handler()
1641 static void ulptx_intr_handler(struct adapter *adapter) in ulptx_intr_handler() argument
1652 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff, in ulptx_intr_handler()
1653 ulptx_intr_info, adapter->irq_stats)) in ulptx_intr_handler()
1654 t3_fatal_err(adapter); in ulptx_intr_handler()
1669 static void pmtx_intr_handler(struct adapter *adapter) in pmtx_intr_handler() argument
1682 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff, in pmtx_intr_handler()
1684 t3_fatal_err(adapter); in pmtx_intr_handler()
1699 static void pmrx_intr_handler(struct adapter *adapter) in pmrx_intr_handler() argument
1712 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff, in pmrx_intr_handler()
1714 t3_fatal_err(adapter); in pmrx_intr_handler()
1720 static void cplsw_intr_handler(struct adapter *adapter) in cplsw_intr_handler() argument
1732 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff, in cplsw_intr_handler()
1734 t3_fatal_err(adapter); in cplsw_intr_handler()
1740 static void mps_intr_handler(struct adapter *adapter) in mps_intr_handler() argument
1747 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff, in mps_intr_handler()
1749 t3_fatal_err(adapter); in mps_intr_handler()
1759 struct adapter *adapter = mc7->adapter; in mc7_intr_handler() local
1760 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); in mc7_intr_handler()
1764 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, " in mc7_intr_handler()
1766 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), in mc7_intr_handler()
1767 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), in mc7_intr_handler()
1768 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), in mc7_intr_handler()
1769 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); in mc7_intr_handler()
1774 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, " in mc7_intr_handler()
1776 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), in mc7_intr_handler()
1777 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), in mc7_intr_handler()
1778 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), in mc7_intr_handler()
1779 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); in mc7_intr_handler()
1784 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n", in mc7_intr_handler()
1791 if (adapter->params.rev > 0) in mc7_intr_handler()
1792 addr = t3_read_reg(adapter, in mc7_intr_handler()
1795 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n", in mc7_intr_handler()
1800 t3_fatal_err(adapter); in mc7_intr_handler()
1802 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
1810 static int mac_intr_handler(struct adapter *adap, unsigned int idx) in mac_intr_handler()
1859 int t3_phy_intr_handler(struct adapter *adapter) in t3_phy_intr_handler() argument
1861 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); in t3_phy_intr_handler()
1863 for_each_port(adapter, i) { in t3_phy_intr_handler()
1864 struct port_info *p = adap2pinfo(adapter, i); in t3_phy_intr_handler()
1869 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { in t3_phy_intr_handler()
1873 t3_link_changed(adapter, i); in t3_phy_intr_handler()
1877 t3_os_phymod_changed(adapter, i); in t3_phy_intr_handler()
1881 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause); in t3_phy_intr_handler()
1888 int t3_slow_intr_handler(struct adapter *adapter) in t3_slow_intr_handler() argument
1890 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0); in t3_slow_intr_handler()
1892 cause &= adapter->slow_intr_mask; in t3_slow_intr_handler()
1896 if (is_pcie(adapter)) in t3_slow_intr_handler()
1897 pcie_intr_handler(adapter); in t3_slow_intr_handler()
1899 pci_intr_handler(adapter); in t3_slow_intr_handler()
1902 t3_sge_err_intr_handler(adapter); in t3_slow_intr_handler()
1904 mc7_intr_handler(&adapter->pmrx); in t3_slow_intr_handler()
1906 mc7_intr_handler(&adapter->pmtx); in t3_slow_intr_handler()
1908 mc7_intr_handler(&adapter->cm); in t3_slow_intr_handler()
1910 cim_intr_handler(adapter); in t3_slow_intr_handler()
1912 tp_intr_handler(adapter); in t3_slow_intr_handler()
1914 ulprx_intr_handler(adapter); in t3_slow_intr_handler()
1916 ulptx_intr_handler(adapter); in t3_slow_intr_handler()
1918 pmrx_intr_handler(adapter); in t3_slow_intr_handler()
1920 pmtx_intr_handler(adapter); in t3_slow_intr_handler()
1922 cplsw_intr_handler(adapter); in t3_slow_intr_handler()
1924 mps_intr_handler(adapter); in t3_slow_intr_handler()
1926 t3_mc5_intr_handler(&adapter->mc5); in t3_slow_intr_handler()
1928 mac_intr_handler(adapter, 0); in t3_slow_intr_handler()
1930 mac_intr_handler(adapter, 1); in t3_slow_intr_handler()
1932 t3_os_ext_intr_handler(adapter); in t3_slow_intr_handler()
1935 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); in t3_slow_intr_handler()
1936 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_slow_intr_handler()
1940 static unsigned int calc_gpio_intr(struct adapter *adap) in calc_gpio_intr()
1959 void t3_intr_enable(struct adapter *adapter) in t3_intr_enable() argument
1976 adapter->slow_intr_mask = PL_INTR_MASK; in t3_intr_enable()
1978 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0); in t3_intr_enable()
1979 t3_write_reg(adapter, A_TP_INT_ENABLE, in t3_intr_enable()
1980 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); in t3_intr_enable()
1982 if (adapter->params.rev > 0) { in t3_intr_enable()
1983 t3_write_reg(adapter, A_CPL_INTR_ENABLE, in t3_intr_enable()
1985 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, in t3_intr_enable()
1989 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK); in t3_intr_enable()
1990 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); in t3_intr_enable()
1993 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); in t3_intr_enable()
1995 if (is_pcie(adapter)) in t3_intr_enable()
1996 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); in t3_intr_enable()
1998 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); in t3_intr_enable()
1999 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); in t3_intr_enable()
2000 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_enable()
2010 void t3_intr_disable(struct adapter *adapter) in t3_intr_disable() argument
2012 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); in t3_intr_disable()
2013 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_disable()
2014 adapter->slow_intr_mask = 0; in t3_intr_disable()
2023 void t3_intr_clear(struct adapter *adapter) in t3_intr_clear() argument
2046 for_each_port(adapter, i) in t3_intr_clear()
2047 t3_port_intr_clear(adapter, i); in t3_intr_clear()
2050 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); in t3_intr_clear()
2052 if (is_pcie(adapter)) in t3_intr_clear()
2053 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); in t3_intr_clear()
2054 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); in t3_intr_clear()
2055 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_intr_clear()
2058 void t3_xgm_intr_enable(struct adapter *adapter, int idx) in t3_xgm_intr_enable() argument
2060 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_enable()
2062 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, in t3_xgm_intr_enable()
2066 void t3_xgm_intr_disable(struct adapter *adapter, int idx) in t3_xgm_intr_disable() argument
2068 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_disable()
2070 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, in t3_xgm_intr_disable()
2082 void t3_port_intr_enable(struct adapter *adapter, int idx) in t3_port_intr_enable() argument
2084 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_enable()
2086 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK); in t3_port_intr_enable()
2087 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ in t3_port_intr_enable()
2099 void t3_port_intr_disable(struct adapter *adapter, int idx) in t3_port_intr_disable() argument
2101 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_disable()
2103 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0); in t3_port_intr_disable()
2104 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */ in t3_port_intr_disable()
2116 static void t3_port_intr_clear(struct adapter *adapter, int idx) in t3_port_intr_clear() argument
2118 struct cphy *phy = &adap2pinfo(adapter, idx)->phy; in t3_port_intr_clear()
2120 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff); in t3_port_intr_clear()
2121 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */ in t3_port_intr_clear()
2136 static int t3_sge_write_context(struct adapter *adapter, unsigned int id, in t3_sge_write_context() argument
2146 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2147 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2148 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); in t3_sge_write_context()
2149 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2151 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2152 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2153 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); in t3_sge_write_context()
2154 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2156 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_write_context()
2158 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_write_context()
2173 static int clear_sge_ctxt(struct adapter *adap, unsigned int id, in clear_sge_ctxt()
2207 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, in t3_sge_init_ecntxt() argument
2216 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_ecntxt()
2220 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | in t3_sge_init_ecntxt()
2222 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | in t3_sge_init_ecntxt()
2225 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); in t3_sge_init_ecntxt()
2227 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_ecntxt()
2231 return t3_sge_write_context(adapter, id, F_EGRESS); in t3_sge_init_ecntxt()
2250 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, in t3_sge_init_flcntxt() argument
2257 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_flcntxt()
2261 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); in t3_sge_init_flcntxt()
2263 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, in t3_sge_init_flcntxt()
2266 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | in t3_sge_init_flcntxt()
2269 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_flcntxt()
2272 return t3_sge_write_context(adapter, id, F_FREELIST); in t3_sge_init_flcntxt()
2290 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, in t3_sge_init_rspcntxt() argument
2298 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_rspcntxt()
2302 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | in t3_sge_init_rspcntxt()
2304 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_rspcntxt()
2308 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_rspcntxt()
2310 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); in t3_sge_init_rspcntxt()
2311 return t3_sge_write_context(adapter, id, F_RESPONSEQ); in t3_sge_init_rspcntxt()
2329 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, in t3_sge_init_cqcntxt() argument
2335 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_cqcntxt()
2339 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); in t3_sge_init_cqcntxt()
2340 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_cqcntxt()
2342 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_cqcntxt()
2346 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | in t3_sge_init_cqcntxt()
2348 return t3_sge_write_context(adapter, id, F_CQ); in t3_sge_init_cqcntxt()
2360 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable) in t3_sge_enable_ecntxt() argument
2362 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_enable_ecntxt()
2365 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_enable_ecntxt()
2366 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_enable_ecntxt()
2367 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_enable_ecntxt()
2368 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID); in t3_sge_enable_ecntxt()
2369 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable)); in t3_sge_enable_ecntxt()
2370 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_enable_ecntxt()
2372 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_enable_ecntxt()
2384 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id) in t3_sge_disable_fl() argument
2386 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_fl()
2389 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_disable_fl()
2390 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_fl()
2391 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE)); in t3_sge_disable_fl()
2392 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_fl()
2393 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0); in t3_sge_disable_fl()
2394 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_fl()
2396 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_fl()
2408 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id) in t3_sge_disable_rspcntxt() argument
2410 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_rspcntxt()
2413 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_rspcntxt()
2414 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_rspcntxt()
2415 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_rspcntxt()
2416 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_rspcntxt()
2417 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_rspcntxt()
2418 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_rspcntxt()
2420 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_rspcntxt()
2432 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id) in t3_sge_disable_cqcntxt() argument
2434 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_cqcntxt()
2437 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_cqcntxt()
2438 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_cqcntxt()
2439 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_cqcntxt()
2440 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_cqcntxt()
2441 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_cqcntxt()
2442 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_cqcntxt()
2444 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_cqcntxt()
2458 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, in t3_sge_cqcntxt_op() argument
2463 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_cqcntxt_op()
2466 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16); in t3_sge_cqcntxt_op()
2467 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) | in t3_sge_cqcntxt_op()
2469 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_cqcntxt_op()
2474 if (adapter->params.rev > 0) in t3_sge_cqcntxt_op()
2477 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2479 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2483 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0)); in t3_sge_cqcntxt_op()
2500 void t3_config_rss(struct adapter *adapter, unsigned int rss_config, in t3_config_rss() argument
2514 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); in t3_config_rss()
2519 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, in t3_config_rss()
2525 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config); in t3_config_rss()
2535 void t3_tp_set_offload_mode(struct adapter *adap, int enable) in t3_tp_set_offload_mode()
2571 static void partition_mem(struct adapter *adap, const struct tp_params *p) in partition_mem()
2629 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr, in tp_wr_indirect()
2636 static void tp_config(struct adapter *adap, const struct tp_params *p) in tp_config()
2701 static void tp_set_timers(struct adapter *adap, unsigned int core_clk) in tp_set_timers()
2745 static int t3_tp_set_coalescing_size(struct adapter *adap, in t3_tp_set_coalescing_size()
2776 static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size) in t3_tp_set_max_rxsize()
2862 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], in t3_load_mtus()
2902 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps) in t3_tp_get_mib_stats()
2919 static void ulp_config(struct adapter *adap, const struct tp_params *p) in ulp_config()
2940 int t3_set_proto_sram(struct adapter *adap, const u8 *data) in t3_set_proto_sram()
2961 void t3_config_trace_filter(struct adapter *adapter, in t3_config_trace_filter() argument
2983 tp_wr_indirect(adapter, addr++, key[0]); in t3_config_trace_filter()
2984 tp_wr_indirect(adapter, addr++, mask[0]); in t3_config_trace_filter()
2985 tp_wr_indirect(adapter, addr++, key[1]); in t3_config_trace_filter()
2986 tp_wr_indirect(adapter, addr++, mask[1]); in t3_config_trace_filter()
2987 tp_wr_indirect(adapter, addr++, key[2]); in t3_config_trace_filter()
2988 tp_wr_indirect(adapter, addr++, mask[2]); in t3_config_trace_filter()
2989 tp_wr_indirect(adapter, addr++, key[3]); in t3_config_trace_filter()
2990 tp_wr_indirect(adapter, addr, mask[3]); in t3_config_trace_filter()
2991 t3_read_reg(adapter, A_TP_PIO_DATA); in t3_config_trace_filter()
3002 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched) in t3_config_sched()
3038 static int tp_init(struct adapter *adap, const struct tp_params *p) in tp_init()
3063 static void chan_init_hw(struct adapter *adap, unsigned int chan_map) in chan_init_hw()
3093 static int calibrate_xgm(struct adapter *adapter) in calibrate_xgm() argument
3095 if (uses_xaui(adapter)) { in calibrate_xgm()
3099 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); in calibrate_xgm()
3100 t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3102 v = t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3104 t3_write_reg(adapter, A_XGM_XAUI_IMP, in calibrate_xgm()
3109 CH_ERR(adapter, "MAC calibration failed\n"); in calibrate_xgm()
3112 t3_write_reg(adapter, A_XGM_RGMII_IMP, in calibrate_xgm()
3114 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm()
3120 static void calibrate_xgm_t3b(struct adapter *adapter) in calibrate_xgm_t3b() argument
3122 if (!uses_xaui(adapter)) { in calibrate_xgm_t3b()
3123 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | in calibrate_xgm_t3b()
3125 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0); in calibrate_xgm_t3b()
3126 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, in calibrate_xgm_t3b()
3128 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm_t3b()
3130 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0); in calibrate_xgm_t3b()
3131 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE); in calibrate_xgm_t3b()
3150 static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val) in wrreg_wait() argument
3152 t3_write_reg(adapter, addr, val); in wrreg_wait()
3153 t3_read_reg(adapter, addr); /* flush */ in wrreg_wait()
3154 if (!(t3_read_reg(adapter, addr) & F_BUSY)) in wrreg_wait()
3156 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr); in wrreg_wait()
3175 struct adapter *adapter = mc7->adapter; in mc7_init() local
3181 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_init()
3186 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3187 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3191 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3192 t3_read_reg(adapter, mc7->offset + A_MC7_CAL); in mc7_init()
3194 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & in mc7_init()
3196 CH_ERR(adapter, "%s MC7 calibration timed out\n", in mc7_init()
3202 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3208 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
3210 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3213 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, in mc7_init()
3218 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
3219 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || in mc7_init()
3220 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || in mc7_init()
3221 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
3225 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
3226 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0); in mc7_init()
3230 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
3231 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
3232 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
3233 wrreg_wait(adapter, mc7->offset + A_MC7_MODE, in mc7_init()
3235 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || in mc7_init()
3236 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
3243 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
3245 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ in mc7_init()
3247 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN); in mc7_init()
3248 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
3249 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
3250 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
3252 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
3253 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ in mc7_init()
3258 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); in mc7_init()
3261 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); in mc7_init()
3266 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); in mc7_init()
3273 static void config_pcie(struct adapter *adap) in config_pcie()
3339 int t3_init_hw(struct adapter *adapter, u32 fw_params) in t3_init_hw() argument
3342 const struct vpd_params *vpd = &adapter->params.vpd; in t3_init_hw()
3344 if (adapter->params.rev > 0) in t3_init_hw()
3345 calibrate_xgm_t3b(adapter); in t3_init_hw()
3346 else if (calibrate_xgm(adapter)) in t3_init_hw()
3350 partition_mem(adapter, &adapter->params.tp); in t3_init_hw()
3352 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3353 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3354 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
3355 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, in t3_init_hw()
3356 adapter->params.mc5.nfilters, in t3_init_hw()
3357 adapter->params.mc5.nroutes)) in t3_init_hw()
3361 if (clear_sge_ctxt(adapter, i, F_CQ)) in t3_init_hw()
3365 if (tp_init(adapter, &adapter->params.tp)) in t3_init_hw()
3368 t3_tp_set_coalescing_size(adapter, in t3_init_hw()
3369 min(adapter->params.sge.max_pkt_size, in t3_init_hw()
3371 t3_tp_set_max_rxsize(adapter, in t3_init_hw()
3372 min(adapter->params.sge.max_pkt_size, 16384U)); in t3_init_hw()
3373 ulp_config(adapter, &adapter->params.tp); in t3_init_hw()
3375 if (is_pcie(adapter)) in t3_init_hw()
3376 config_pcie(adapter); in t3_init_hw()
3378 t3_set_reg_field(adapter, A_PCIX_CFG, 0, in t3_init_hw()
3381 if (adapter->params.rev == T3_REV_C) in t3_init_hw()
3382 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, in t3_init_hw()
3385 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); in t3_init_hw()
3386 t3_write_reg(adapter, A_PM1_RX_MODE, 0); in t3_init_hw()
3387 t3_write_reg(adapter, A_PM1_TX_MODE, 0); in t3_init_hw()
3388 chan_init_hw(adapter, adapter->params.chan_map); in t3_init_hw()
3389 t3_sge_init(adapter, &adapter->params.sge); in t3_init_hw()
3390 t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN); in t3_init_hw()
3392 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); in t3_init_hw()
3394 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
3395 t3_write_reg(adapter, A_CIM_BOOT_CFG, in t3_init_hw()
3397 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ in t3_init_hw()
3402 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); in t3_init_hw()
3404 CH_ERR(adapter, "uP initialization timed out\n"); in t3_init_hw()
3421 static void get_pci_mode(struct adapter *adapter, struct pci_params *p) in get_pci_mode() argument
3426 if (pci_is_pcie(adapter->pdev)) { in get_pci_mode()
3430 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); in get_pci_mode()
3435 pci_mode = t3_read_reg(adapter, A_PCIX_MODE); in get_pci_mode()
3492 static void mc7_prep(struct adapter *adapter, struct mc7 *mc7, in mc7_prep() argument
3497 mc7->adapter = adapter; in mc7_prep()
3500 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_prep()
3505 static void mac_prep(struct cmac *mac, struct adapter *adapter, int index) in mac_prep() argument
3509 mac->adapter = adapter; in mac_prep()
3510 pci_read_config_word(adapter->pdev, 0x2, &devid); in mac_prep()
3512 if (devid == 0x37 && !adapter->params.vpd.xauicfg[1]) in mac_prep()
3517 if (adapter->params.rev == 0 && uses_xaui(adapter)) { in mac_prep()
3518 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, in mac_prep()
3519 is_10G(adapter) ? 0x2901c04 : 0x2301c04); in mac_prep()
3520 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset, in mac_prep()
3525 static void early_hw_init(struct adapter *adapter, in early_hw_init() argument
3528 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2); in early_hw_init()
3530 mi1_init(adapter, ai); in early_hw_init()
3531 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ in early_hw_init()
3532 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); in early_hw_init()
3533 t3_write_reg(adapter, A_T3DBG_GPIO_EN, in early_hw_init()
3535 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); in early_hw_init()
3536 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); in early_hw_init()
3538 if (adapter->params.rev == 0 || !uses_xaui(adapter)) in early_hw_init()
3542 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3543 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3546 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3547 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3548 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); in early_hw_init()
3549 t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
3557 int t3_reset_adapter(struct adapter *adapter) in t3_reset_adapter() argument
3560 adapter->params.rev < T3_REV_B2 && is_pcie(adapter); in t3_reset_adapter()
3564 pci_save_state(adapter->pdev); in t3_reset_adapter()
3565 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); in t3_reset_adapter()
3573 pci_read_config_word(adapter->pdev, 0x00, &devid); in t3_reset_adapter()
3582 pci_restore_state(adapter->pdev); in t3_reset_adapter()
3586 static int init_parity(struct adapter *adap) in init_parity()
3621 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, in t3_prep_adapter() argument
3627 get_pci_mode(adapter, &adapter->params.pci); in t3_prep_adapter()
3629 adapter->params.info = ai; in t3_prep_adapter()
3630 adapter->params.nports = ai->nports0 + ai->nports1; in t3_prep_adapter()
3631 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1); in t3_prep_adapter()
3632 adapter->params.rev = t3_read_reg(adapter, A_PL_REV); in t3_prep_adapter()
3641 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
3642 adapter->params.stats_update_period = is_10G(adapter) ? in t3_prep_adapter()
3644 adapter->params.pci.vpd_cap_addr = in t3_prep_adapter()
3645 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD); in t3_prep_adapter()
3646 ret = get_vpd_params(adapter, &adapter->params.vpd); in t3_prep_adapter()
3650 if (reset && t3_reset_adapter(adapter)) in t3_prep_adapter()
3653 t3_sge_prep(adapter, &adapter->params.sge); in t3_prep_adapter()
3655 if (adapter->params.vpd.mclk) { in t3_prep_adapter()
3656 struct tp_params *p = &adapter->params.tp; in t3_prep_adapter()
3658 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX"); in t3_prep_adapter()
3659 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); in t3_prep_adapter()
3660 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); in t3_prep_adapter()
3662 p->nchan = adapter->params.chan_map == 3 ? 2 : 1; in t3_prep_adapter()
3663 p->pmrx_size = t3_mc7_size(&adapter->pmrx); in t3_prep_adapter()
3664 p->pmtx_size = t3_mc7_size(&adapter->pmtx); in t3_prep_adapter()
3665 p->cm_size = t3_mc7_size(&adapter->cm); in t3_prep_adapter()
3669 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; in t3_prep_adapter()
3673 adapter->params.rev > 0 ? 12 : 6; in t3_prep_adapter()
3676 adapter->params.offload = t3_mc7_size(&adapter->pmrx) && in t3_prep_adapter()
3677 t3_mc7_size(&adapter->pmtx) && in t3_prep_adapter()
3678 t3_mc7_size(&adapter->cm); in t3_prep_adapter()
3680 if (is_offload(adapter)) { in t3_prep_adapter()
3681 adapter->params.mc5.nservers = DEFAULT_NSERVERS; in t3_prep_adapter()
3682 adapter->params.mc5.nfilters = adapter->params.rev > 0 ? in t3_prep_adapter()
3684 adapter->params.mc5.nroutes = 0; in t3_prep_adapter()
3685 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); in t3_prep_adapter()
3687 init_mtus(adapter->params.mtus); in t3_prep_adapter()
3688 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t3_prep_adapter()
3691 early_hw_init(adapter, ai); in t3_prep_adapter()
3692 ret = init_parity(adapter); in t3_prep_adapter()
3696 for_each_port(adapter, i) { in t3_prep_adapter()
3699 struct port_info *p = adap2pinfo(adapter, i); in t3_prep_adapter()
3701 while (!adapter->params.vpd.port_type[++j]) in t3_prep_adapter()
3704 pti = &port_types[adapter->params.vpd.port_type[j]]; in t3_prep_adapter()
3706 CH_ALERT(adapter, "Invalid port type index %d\n", in t3_prep_adapter()
3707 adapter->params.vpd.port_type[j]); in t3_prep_adapter()
3711 p->phy.mdio.dev = adapter->port[i]; in t3_prep_adapter()
3712 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j, in t3_prep_adapter()
3716 mac_prep(&p->mac, adapter, j); in t3_prep_adapter()
3723 memcpy(hw_addr, adapter->params.vpd.eth_base, 5); in t3_prep_adapter()
3724 hw_addr[5] = adapter->params.vpd.eth_base[5] + i; in t3_prep_adapter()
3726 memcpy(adapter->port[i]->dev_addr, hw_addr, in t3_prep_adapter()
3737 adapter->params.linkpoll_period > 10) in t3_prep_adapter()
3738 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
3744 void t3_led_ready(struct adapter *adapter) in t3_led_ready() argument
3746 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, in t3_led_ready()
3750 int t3_replay_prep_adapter(struct adapter *adapter) in t3_replay_prep_adapter() argument
3752 const struct adapter_info *ai = adapter->params.info; in t3_replay_prep_adapter()
3756 early_hw_init(adapter, ai); in t3_replay_prep_adapter()
3757 ret = init_parity(adapter); in t3_replay_prep_adapter()
3761 for_each_port(adapter, i) { in t3_replay_prep_adapter()
3763 struct port_info *p = adap2pinfo(adapter, i); in t3_replay_prep_adapter()
3765 while (!adapter->params.vpd.port_type[++j]) in t3_replay_prep_adapter()
3768 pti = &port_types[adapter->params.vpd.port_type[j]]; in t3_replay_prep_adapter()
3769 ret = pti->phy_prep(&p->phy, adapter, p->phy.mdio.prtad, NULL); in t3_replay_prep_adapter()