Lines Matching refs:adapter

10 	adapter_t *adapter;  member
58 struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p) in t1_tp_create() argument
65 tp->adapter = adapter; in t1_tp_create()
72 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()
75 if (!t1_is_asic(tp->adapter)) { in t1_tp_intr_enable()
78 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_enable()
80 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()
85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
87 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_enable()
93 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()
96 if (!t1_is_asic(tp->adapter)) { in t1_tp_intr_disable()
98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable()
100 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()
104 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_disable()
106 tp->adapter->regs + A_PL_ENABLE); in t1_tp_intr_disable()
113 if (!t1_is_asic(tp->adapter)) { in t1_tp_intr_clear()
115 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); in t1_tp_intr_clear()
116 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE); in t1_tp_intr_clear()
120 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE); in t1_tp_intr_clear()
121 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE); in t1_tp_intr_clear()
130 if (!t1_is_asic(tp->adapter)) in t1_tp_intr_handler()
134 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE); in t1_tp_intr_handler()
135 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE); in t1_tp_intr_handler()
141 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG); in set_csum_offload()
147 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG); in set_csum_offload()
166 adapter_t *adapter = tp->adapter; in t1_tp_reset() local
168 tp_init(adapter, p, tp_clk); in t1_tp_reset()
169 writel(F_TP_RESET, adapter->regs + A_TP_RESET); in t1_tp_reset()