Lines Matching refs:rb
58 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
60 static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
260 void __iomem *rb; in bfa_ioc_ct_reg_init() local
263 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
265 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
266 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
267 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
270 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
271 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
272 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
273 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
274 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
275 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
276 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
278 ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG; in bfa_ioc_ct_reg_init()
279 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
280 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
281 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
282 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
283 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
284 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
290 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct_reg_init()
291 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct_reg_init()
292 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct_reg_init()
293 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct_reg_init()
298 ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG; in bfa_ioc_ct_reg_init()
299 ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG; in bfa_ioc_ct_reg_init()
300 ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG; in bfa_ioc_ct_reg_init()
301 ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT; in bfa_ioc_ct_reg_init()
302 ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC; in bfa_ioc_ct_reg_init()
307 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct_reg_init()
313 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
319 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
322 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
324 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
325 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
326 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
327 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
328 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
329 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
332 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
333 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
334 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
335 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
336 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
338 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG; in bfa_ioc_ct2_reg_init()
339 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
340 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
341 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
342 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
348 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct2_reg_init()
349 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct2_reg_init()
350 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
351 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
356 ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG; in bfa_ioc_ct2_reg_init()
357 ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG; in bfa_ioc_ct2_reg_init()
358 ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG; in bfa_ioc_ct2_reg_init()
359 ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT; in bfa_ioc_ct2_reg_init()
360 ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC; in bfa_ioc_ct2_reg_init()
365 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct2_reg_init()
371 ioc->ioc_regs.err_set = rb + ERR_SET_REG; in bfa_ioc_ct2_reg_init()
380 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
386 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
395 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
398 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
406 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
409 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
428 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
456 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_nw_ioc_ct2_poweron() local
459 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
462 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
468 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
470 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
610 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct_pll_init() argument
625 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
629 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
631 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
633 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
635 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
636 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
637 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
638 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
639 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
640 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
641 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
642 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
645 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
648 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
651 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
654 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
655 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
657 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
658 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
661 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
664 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
667 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
668 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
670 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
672 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
675 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
676 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
679 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
681 r32 = readl((rb + MBIST_STAT_REG)); in bfa_ioc_ct_pll_init()
682 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
687 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
694 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
698 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
704 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
706 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
711 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
713 (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
715 r32 = readl((rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
717 (rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
722 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
725 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
739 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
746 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
750 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
755 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
756 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
761 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
762 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
767 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
770 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
779 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
783 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
785 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
788 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
790 writel(0, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
794 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
798 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_mac_reset()
799 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_mac_reset()
804 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
806 (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
811 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
813 (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
817 (rb + CT2_CSI_MAC_CONTROL_REG(0))); in bfa_ioc_ct2_mac_reset()
819 (rb + CT2_CSI_MAC_CONTROL_REG(1))); in bfa_ioc_ct2_mac_reset()
827 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
831 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
839 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
844 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
846 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
855 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct2_pll_init() argument
860 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
862 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
866 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_pll_init()
867 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_pll_init()
869 rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_pll_init()
872 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
879 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
886 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_pll_init()
889 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG)); in bfa_ioc_ct2_pll_init()
891 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_pll_init()
897 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
898 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_pll_init()
899 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_pll_init()
902 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_pll_init()
904 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
905 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_pll_init()
907 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
912 r32 = readl((rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_pll_init()
913 writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
914 r32 = readl((rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_pll_init()
915 writel(r32 | 1, rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
922 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
923 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
926 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
928 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
930 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
931 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
933 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
935 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
936 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
940 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
942 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); in bfa_ioc_ct2_pll_init()
943 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); in bfa_ioc_ct2_pll_init()