Lines Matching refs:tr32
624 #define tr32(reg) tp->read32(tp, reg) macro
670 *val = tr32(TG3PCI_MEM_WIN_DATA); in tg3_read_mem()
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
1137 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1141 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1199 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1202 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1431 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1450 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1463 val = tr32(MAC_EXT_RGMII_MODE); in tg3_mdio_config_5785()
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; in tg3_mdio_init()
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) & in tg3_mdio_init()
1621 val = tr32(GRC_RX_CPU_EVENT); in tg3_generate_fw_event()
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
2378 val = tr32(TG3_CPMU_EEE_MODE); in tg3_eee_pull_config()
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2420 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_adjust()
2440 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_enable()
2638 val = tr32(GRC_MISC_CFG); in tg3_phy_reset()
2664 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_phy_reset()
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_phy_reset()
2797 status = tr32(TG3_CPMU_DRV_STATUS); in tg3_set_function_status()
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_power_down_phy()
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG); in tg3_power_down_phy()
3081 val = tr32(GRC_MISC_CFG); in tg3_power_down_phy()
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_power_down_phy()
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
3171 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_enable_nvram_access()
3181 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_disable_nvram_access()
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
3207 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
3216 tmp = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
3307 *val = tr32(NVRAM_RDDATA); in tg3_nvram_read()
3348 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3360 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3553 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3564 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_halt_cpu()
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); in tg3_load_firmware_cpu()
3774 if (tr32(cpu_base + CPU_PC) == pc) in tg3_pause_cpu_and_set_pc()
3817 tr32(RX_CPU_BASE + CPU_PC), in tg3_load_5701_a0_firmware_fix()
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) in tg3_validate_rxcpu_state()
3940 __func__, tr32(cpu_base + CPU_PC), in tg3_load_tso_firmware()
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_power_down_prepare()
4101 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_power_down_prepare()
4242 u32 val = tr32(0x7d00); in tg3_power_down_prepare()
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_autoneg_cfg()
5000 u32 led_ctrl = tr32(MAC_LED_CTRL); in tg3_setup_copper_phy()
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
5444 u32 mac_status = tr32(MAC_STATUS); in tg3_init_bcm8002()
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_setup_fiber_hw_autoneg()
5570 sg_dig_status = tr32(SG_DIG_STATUS); in tg3_setup_fiber_hw_autoneg()
5571 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5615 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5674 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
5680 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_by_hand()
5718 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5747 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
5768 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; in tg3_setup_phy()
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; in tg3_setup_phy()
6091 val |= tr32(MAC_TX_LENGTHS) & in tg3_setup_phy()
6113 val = tr32(PCIE_PWR_MGMT_THRESH); in tg3_setup_phy()
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB); in tg3_refclk_read()
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32; in tg3_refclk_read()
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write()
6264 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6377 *dst++ = tr32(off + i); in tg3_rd32_loop()
6442 regs[i / sizeof(u32)] = tr32(i); in tg3_dump_state()
6544 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB); in tg3_tx()
6545 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32; in tg3_tx()
6857 tstamp = tr32(TG3_RX_TSTAMP_LSB); in tg3_rx()
6858 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32; in tg3_rx()
7280 val = tr32(HOSTCC_FLOW_ATTN); in tg3_process_error()
7286 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { in tg3_process_error()
7291 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { in tg3_process_error()
7507 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt()
7556 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt_tagged()
7602 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_test_isr()
8825 val = tr32(ofs); in tg3_stop_block()
8839 val = tr32(ofs); in tg3_stop_block()
8896 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
8902 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); in tg3_abort_hw()
8987 val = tr32(MSGINT_MODE); in tg3_restore_pci_state()
8999 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_override_clk()
9020 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_restore_clk()
9027 val = tr32(TG3_CPMU_CLCK_ORIDE); in tg3_restore_clk()
9103 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_chip_reset()
9114 tr32(TG3_PCIE_PHY_TSTCTL) == in tg3_chip_reset()
9125 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
9127 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_chip_reset()
9212 val = tr32(MEMARB_MODE); in tg3_chip_reset()
9237 val = tr32(0xc4); in tg3_chip_reset()
9270 val = tr32(0x7c00); in tg3_chip_reset()
9356 addr0_high = tr32(MAC_ADDR_0_HIGH); in tg3_set_mac_addr()
9357 addr0_low = tr32(MAC_ADDR_0_LOW); in tg3_set_mac_addr()
9358 addr1_high = tr32(MAC_ADDR_1_HIGH); in tg3_set_mac_addr()
9359 addr1_low = tr32(MAC_ADDR_1_LOW); in tg3_set_mac_addr()
9870 val = tr32(TG3_CPMU_CTRL); in tg3_reset_hw()
9874 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9879 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); in tg3_reset_hw()
9884 val = tr32(TG3_CPMU_HST_ACC); in tg3_reset_hw()
9891 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; in tg3_reset_hw()
9896 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; in tg3_reset_hw()
9901 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_reset_hw()
9906 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9912 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw()
9921 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9927 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9939 val = tr32(TG3_CPMU_PADRNG_CTL); in tg3_reset_hw()
9943 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9949 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9958 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9977 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
9986 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
9995 val = tr32(TG3PCI_MSI_DATA); in tg3_reset_hw()
10010 val = tr32(TG3PCI_DMA_RW_CTRL) & in tg3_reset_hw()
10052 val = tr32(GRC_MISC_CFG); in tg3_reset_hw()
10109 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
10119 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10214 val |= tr32(MAC_TX_LENGTHS) & in tg3_reset_hw()
10248 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10277 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; in tg3_reset_hw()
10291 val = tr32(tgtreg); in tg3_reset_hw()
10314 val = tr32(tgtreg); in tg3_reset_hw()
10322 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10327 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10342 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
10418 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10429 val = tr32(MSGINT_MODE); in tg3_reset_hw()
10455 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10493 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10497 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_reset_hw()
10560 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10610 val = tr32(MAC_SERDES_CFG); in tg3_reset_hw()
10638 tmp = tr32(SERDES_RX_CTRL); in tg3_reset_hw()
10830 do { u32 __val = tr32(REG); \
10861 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_periodic_fetch_stats()
10889 u32 val = tr32(HOSTCC_FLOW_ATTN); in tg3_periodic_fetch_stats()
10942 tr32(HOSTCC_MODE); in tg3_timer()
10958 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
10977 mac_stat = tr32(MAC_STATUS); in tg3_timer()
10989 u32 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11016 u32 cpmu = tr32(TG3_CPMU_STATUS); in tg3_timer()
11231 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11250 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_test_interrupt()
11277 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11471 u32 msi_mode = tr32(MSGINT_MODE); in tg3_ints_init()
11570 u32 val = tr32(PCIE_TRANSACTION_CFG); in tg3_start()
11956 cpmu_val = tr32(TG3_CPMU_CTRL); in tg3_get_eeprom()
13207 save_val = tr32(offset); in tg3_test_registers()
13217 val = tr32(offset); in tg3_test_registers()
13229 val = tr32(offset); in tg3_test_registers()
13645 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_test_loopback()
14333 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_nvram_info()
14411 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5752_nvram_info()
14452 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5755_nvram_info()
14508 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5787_nvram_info()
14546 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5761_nvram_info()
14586 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14628 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_57780_nvram_info()
14701 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5717_nvram_info()
14779 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5720_nvram_info()
14942 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
15092 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
15096 val = tr32(VCPU_CFGSHDW); in tg3_get_eeprom_hw_cfg()
15340 val = tr32(OTP_STATUS); in tg3_issue_otp_command()
15367 thalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
15374 bhalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
16114 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; in tg3_10_100_only_device()
16566 val = tr32(MEMARB_MODE); in tg3_get_invariants()
16583 val = tr32(TG3_CPMU_STATUS); in tg3_get_invariants()
16659 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16751 val = tr32(GRC_MODE); in tg3_get_invariants()
16804 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
16906 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16959 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
16998 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
16999 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
17231 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17233 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17285 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
17520 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
17525 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == in tg3_bus_string()
17806 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { in tg3_init_one()
17867 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
17868 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_init_one()