Lines Matching refs:tg3_writephy
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() function
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1352 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
2209 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2267 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2274 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2571 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2578 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2728 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
3090 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3091 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3094 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3098 tg3_writephy(tp, in tg3_power_down_phy()
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4441 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4491 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4837 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
5453 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5464 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5467 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5469 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5470 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5473 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5477 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5479 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5489 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5891 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5893 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5924 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5925 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5931 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6033 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
8212 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8216 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8221 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8231 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8262 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
10659 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
11750 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
12324 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
15546 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()