277 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
287 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
288 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
312 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
313 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
322 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
323 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
499 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
508 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
537 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
556 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
565 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
586 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
603 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
618 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
623 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
627 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
1304 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1307 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1343 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1350 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1358 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1361 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1952 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1953 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
2281 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2386 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2423 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2455 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2558 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2576 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2579 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2581 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2631 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2632 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2652 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2697 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2702 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2790 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2792 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
3288 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3306 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3354 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3422 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3424 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3463 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3502 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3540 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3545 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3550 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3590 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3613 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3639 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3642 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3643 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3644 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3785 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3787 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3791 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3801 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3804 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3807 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3813 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3816 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3980 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
3984 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
3987 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
3990 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
3991 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
3992 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
3995 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
4002 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4042 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4046 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4092 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4114 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4137 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4142 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4143 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4166 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4177 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4188 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4208 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4211 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4214 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4250 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4253 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4256 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4296 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4301 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4304 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4307 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4374 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4375 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4376 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4377 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4738 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4740 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4741 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4755 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_reset_chip()
4765 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_reset_chip()
4789 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4796 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4804 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4853 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4862 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4876 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4897 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4902 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4914 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4944 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4947 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4948 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4951 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4957 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4965 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4972 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4988 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
4990 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
4992 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
4994 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
4996 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
4999 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5002 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5005 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5008 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5010 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5012 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5015 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5019 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5021 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5022 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5032 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5041 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5052 		BNX2_WR(bp, base,  in bnx2_init_chip()
5057 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5061 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5064 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5068 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5073 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5075 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5083 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5088 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5230 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5250 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5290 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5301 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5306 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5309 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5323 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5324 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5335 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5826 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5848 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5852 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
6007 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6174 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6247 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6248 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6249 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6503 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6504 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6506 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6690 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
7686 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7690 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7699 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7703 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7704 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
8145 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8216 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()