278 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
316 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
496 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
500 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
513 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
517 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
534 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
538 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
553 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
557 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
570 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
583 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
587 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
606 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
1311 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1353 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1564 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
2420 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2449 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2560 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2585 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
3350 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3361 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3417 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3465 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3965 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
4000 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4039 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4044 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4094 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4117 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4136 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4149 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4165 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4175 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4186 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4222 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4264 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4266 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4313 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4335 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4760 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_reset_chip()
4763 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4766 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4770 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_reset_chip()
4786 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4790 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4816 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4831 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4900 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4935 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4954 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
5081 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5089 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5093 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5229 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5829 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5855 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
6004 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6008 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6011 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6253 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6498 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6507 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6511 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6512 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6513 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6534 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6535 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6537 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6539 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6542 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
7069 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7685 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7915 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7955 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7961 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
8149 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8214 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8373 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()