213 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )  in bmwrite()  function
248 		bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
252 		bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
255 	bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
257 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
269 		bmwrite(dev, MIFCSR, b);  in bmac_mif_writebits()
271 		bmwrite(dev, MIFCSR, b|1);  in bmac_mif_writebits()
281 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
286 	bmwrite(dev, MIFCSR, 2);  in bmac_mif_read()
288 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_read()
291 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
299 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_write()
319 	bmwrite(dev, RXRST, RxResetValue);  in bmac_init_registers()
320 	bmwrite(dev, TXRST, TxResetBit);  in bmac_init_registers()
332 		bmwrite(dev, XCVRIF, regValue);  in bmac_init_registers()
336 	bmwrite(dev, RSEED, (unsigned short)0x1968);  in bmac_init_registers()
340 	bmwrite(dev, XIFC, regValue);  in bmac_init_registers()
345 	bmwrite(dev, NCCNT, 0);  in bmac_init_registers()
346 	bmwrite(dev, NTCNT, 0);  in bmac_init_registers()
347 	bmwrite(dev, EXCNT, 0);  in bmac_init_registers()
348 	bmwrite(dev, LTCNT, 0);  in bmac_init_registers()
351 	bmwrite(dev, FRCNT, 0);  in bmac_init_registers()
352 	bmwrite(dev, LECNT, 0);  in bmac_init_registers()
353 	bmwrite(dev, AECNT, 0);  in bmac_init_registers()
354 	bmwrite(dev, FECNT, 0);  in bmac_init_registers()
355 	bmwrite(dev, RXCV, 0);  in bmac_init_registers()
358 	bmwrite(dev, TXTH, 4);	/* 4 octets before tx starts */  in bmac_init_registers()
360 	bmwrite(dev, TXFIFOCSR, 0);	/* first disable txFIFO */  in bmac_init_registers()
361 	bmwrite(dev, TXFIFOCSR, TxFIFOEnable );  in bmac_init_registers()
364 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_init_registers()
365 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_init_registers()
372 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); 	/* bits 15 - 0 */  in bmac_init_registers()
373 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); 	/* bits 31 - 16 */  in bmac_init_registers()
374 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); 	/* bits 47 - 32 */  in bmac_init_registers()
375 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); 	/* bits 63 - 48 */  in bmac_init_registers()
378 	bmwrite(dev, MADD0, *pWord16++);  in bmac_init_registers()
379 	bmwrite(dev, MADD1, *pWord16++);  in bmac_init_registers()
380 	bmwrite(dev, MADD2, *pWord16);  in bmac_init_registers()
382 	bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);  in bmac_init_registers()
384 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_init_registers()
391 	bmwrite(dev, INTDISABLE, DisableAll);
397 	bmwrite(dev, INTDISABLE, EnableNormal);
413 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_start_chip()
417 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_start_chip()
481 		bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_suspend()
483        		bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_suspend()
484 		bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_suspend()
540 	bmwrite(dev, MADD0, *pWord16++);  in bmac_set_address()
541 	bmwrite(dev, MADD1, *pWord16++);  in bmac_set_address()
542 	bmwrite(dev, MADD2, *pWord16);  in bmac_set_address()
909 	bmwrite(dev, RXCFG, rx_cfg);  in bmac_rx_off()
926 	bmwrite(dev, RXRST, RxResetValue);  in bmac_rx_on()
927 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_rx_on()
928 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_rx_on()
929 	bmwrite(dev, RXCFG, rx_cfg );  in bmac_rx_on()
936 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */  in bmac_update_hash_table_mask()
937 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */  in bmac_update_hash_table_mask()
938 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */  in bmac_update_hash_table_mask()
939 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */  in bmac_update_hash_table_mask()
993 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1023 		bmwrite(dev, BHASH0, 0xffff);  in bmac_set_multicast()
1024 		bmwrite(dev, BHASH1, 0xffff);  in bmac_set_multicast()
1025 		bmwrite(dev, BHASH2, 0xffff);  in bmac_set_multicast()
1026 		bmwrite(dev, BHASH3, 0xffff);  in bmac_set_multicast()
1030 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1036 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1043 		bmwrite(dev, BHASH0, hash_table[0]);  in bmac_set_multicast()
1044 		bmwrite(dev, BHASH1, hash_table[1]);  in bmac_set_multicast()
1045 		bmwrite(dev, BHASH2, hash_table[2]);  in bmac_set_multicast()
1046 		bmwrite(dev, BHASH3, hash_table[3]);  in bmac_set_multicast()
1098 	bmwrite(dev, SROMCSR, ChipSelect | Clk);  in bmac_clock_out_bit()
1105 	bmwrite(dev, SROMCSR, ChipSelect);  in bmac_clock_out_bit()
1119 	bmwrite(dev, SROMCSR, data | ChipSelect  );  in bmac_clock_in_bit()
1122 	bmwrite(dev, SROMCSR, data | ChipSelect | Clk );  in bmac_clock_in_bit()
1125 	bmwrite(dev, SROMCSR, data | ChipSelect);  in bmac_clock_in_bit()
1133 	bmwrite(dev, SROMCSR, 0);  in reset_and_select_srom()
1161 	bmwrite(dev, SROMCSR, 0);  in read_srom()
1212 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_reset_and_enable()
1293 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1301 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1406 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_close()
1409 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_close()
1411 	bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_close()
1501 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_tx_timeout()
1503 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_tx_timeout()
1540 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_tx_timeout()
1542 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_tx_timeout()