25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,  in xgene_enet_wr_csr()  argument
28 	void __iomem *addr = pdata->eth_csr_addr + offset;  in xgene_enet_wr_csr()
33 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,  in xgene_enet_wr_ring_if()  argument
36 	void __iomem *addr = pdata->eth_ring_if_addr + offset;  in xgene_enet_wr_ring_if()
41 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,  in xgene_enet_wr_diag_csr()  argument
44 	void __iomem *addr = pdata->eth_diag_csr_addr + offset;  in xgene_enet_wr_diag_csr()
72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,  in xgene_enet_wr_mac()  argument
77 	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;  in xgene_enet_wr_mac()
78 	wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;  in xgene_enet_wr_mac()
79 	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;  in xgene_enet_wr_mac()
80 	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;  in xgene_enet_wr_mac()
83 		netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",  in xgene_enet_wr_mac()
87 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,  in xgene_enet_rd_csr()  argument
90 	void __iomem *addr = pdata->eth_csr_addr + offset;  in xgene_enet_rd_csr()
95 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,  in xgene_enet_rd_diag_csr()  argument
98 	void __iomem *addr = pdata->eth_diag_csr_addr + offset;  in xgene_enet_rd_diag_csr()
126 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,  in xgene_enet_rd_mac()  argument
131 	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;  in xgene_enet_rd_mac()
132 	rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;  in xgene_enet_rd_mac()
133 	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;  in xgene_enet_rd_mac()
134 	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;  in xgene_enet_rd_mac()
137 		netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",  in xgene_enet_rd_mac()
141 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)  in xgene_enet_ecc_init()  argument
143 	struct net_device *ndev = pdata->ndev;  in xgene_enet_ecc_init()
147 	xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);  in xgene_enet_ecc_init()
150 		xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);  in xgene_enet_ecc_init()
161 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)  in xgene_enet_config_ring_if_assoc()  argument
163 	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);  in xgene_enet_config_ring_if_assoc()
164 	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);  in xgene_enet_config_ring_if_assoc()
165 	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);  in xgene_enet_config_ring_if_assoc()
166 	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);  in xgene_enet_config_ring_if_assoc()
169 static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)  in xgene_xgmac_reset()  argument
171 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);  in xgene_xgmac_reset()
172 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);  in xgene_xgmac_reset()
175 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)  in xgene_xgmac_set_mac_addr()  argument
178 	u8 *dev_addr = pdata->ndev->dev_addr;  in xgene_xgmac_set_mac_addr()
184 	xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);  in xgene_xgmac_set_mac_addr()
185 	xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);  in xgene_xgmac_set_mac_addr()
188 static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)  in xgene_enet_link_status()  argument
192 	xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);  in xgene_enet_link_status()
197 static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)  in xgene_xgmac_init()  argument
201 	xgene_xgmac_reset(pdata);  in xgene_xgmac_init()
203 	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);  in xgene_xgmac_init()
206 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);  in xgene_xgmac_init()
208 	xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600);  in xgene_xgmac_init()
209 	xgene_xgmac_set_mac_addr(pdata);  in xgene_xgmac_init()
211 	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);  in xgene_xgmac_init()
213 	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);  in xgene_xgmac_init()
215 	xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);  in xgene_xgmac_init()
216 	xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);  in xgene_xgmac_init()
217 	xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);  in xgene_xgmac_init()
219 	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);  in xgene_xgmac_init()
220 	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);  in xgene_xgmac_init()
223 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)  in xgene_xgmac_rx_enable()  argument
227 	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);  in xgene_xgmac_rx_enable()
228 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);  in xgene_xgmac_rx_enable()
231 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)  in xgene_xgmac_tx_enable()  argument
235 	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);  in xgene_xgmac_tx_enable()
236 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);  in xgene_xgmac_tx_enable()
239 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)  in xgene_xgmac_rx_disable()  argument
243 	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);  in xgene_xgmac_rx_disable()
244 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);  in xgene_xgmac_rx_disable()
247 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)  in xgene_xgmac_tx_disable()  argument
251 	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);  in xgene_xgmac_tx_disable()
252 	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);  in xgene_xgmac_tx_disable()
255 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)  in xgene_enet_reset()  argument
257 	if (!xgene_ring_mgr_init(pdata))  in xgene_enet_reset()
260 	clk_prepare_enable(pdata->clk);  in xgene_enet_reset()
261 	clk_disable_unprepare(pdata->clk);  in xgene_enet_reset()
262 	clk_prepare_enable(pdata->clk);  in xgene_enet_reset()
264 	xgene_enet_ecc_init(pdata);  in xgene_enet_reset()
265 	xgene_enet_config_ring_if_assoc(pdata);  in xgene_enet_reset()
270 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,  in xgene_enet_xgcle_bypass()  argument
275 	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);  in xgene_enet_xgcle_bypass()
278 	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);  in xgene_enet_xgcle_bypass()
281 	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);  in xgene_enet_xgcle_bypass()
284 	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);  in xgene_enet_xgcle_bypass()
287 static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)  in xgene_enet_shutdown()  argument
289 	clk_disable_unprepare(pdata->clk);  in xgene_enet_shutdown()
294 	struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),  in xgene_enet_link_state()  local
296 	struct net_device *ndev = pdata->ndev;  in xgene_enet_link_state()
299 	link_status = xgene_enet_link_status(pdata);  in xgene_enet_link_state()
303 			xgene_xgmac_init(pdata);  in xgene_enet_link_state()
304 			xgene_xgmac_rx_enable(pdata);  in xgene_enet_link_state()
305 			xgene_xgmac_tx_enable(pdata);  in xgene_enet_link_state()
311 			xgene_xgmac_rx_disable(pdata);  in xgene_enet_link_state()
312 			xgene_xgmac_tx_disable(pdata);  in xgene_enet_link_state()
319 	schedule_delayed_work(&pdata->link_work, poll_interval);  in xgene_enet_link_state()