Lines Matching refs:p
25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) in xgene_enet_wr_csr() argument
27 iowrite32(val, p->eth_csr_addr + offset); in xgene_enet_wr_csr()
30 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p, in xgene_enet_wr_ring_if() argument
33 iowrite32(val, p->eth_ring_if_addr + offset); in xgene_enet_wr_ring_if()
36 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p, in xgene_enet_wr_diag_csr() argument
39 iowrite32(val, p->eth_diag_csr_addr + offset); in xgene_enet_wr_diag_csr()
63 static void xgene_enet_wr_mac(struct xgene_enet_pdata *p, in xgene_enet_wr_mac() argument
67 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, in xgene_enet_wr_mac()
68 .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, in xgene_enet_wr_mac()
69 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, in xgene_enet_wr_mac()
70 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET in xgene_enet_wr_mac()
74 netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr); in xgene_enet_wr_mac()
77 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() argument
79 return ioread32(p->eth_csr_addr + offset); in xgene_enet_rd_csr()
82 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_diag_csr() argument
84 return ioread32(p->eth_diag_csr_addr + offset); in xgene_enet_rd_diag_csr()
111 static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr) in xgene_enet_rd_mac() argument
114 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, in xgene_enet_rd_mac()
115 .ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET, in xgene_enet_rd_mac()
116 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, in xgene_enet_rd_mac()
117 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET in xgene_enet_rd_mac()
123 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) in xgene_enet_ecc_init() argument
125 struct net_device *ndev = p->ndev; in xgene_enet_ecc_init()
129 xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); in xgene_enet_ecc_init()
132 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); in xgene_enet_ecc_init()
141 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) in xgene_enet_config_ring_if_assoc() argument
145 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
146 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
149 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, in xgene_mii_phy_write() argument
156 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
159 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
162 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_write()
168 netdev_err(p->ndev, "MII_MGMT write failed\n"); in xgene_mii_phy_write()
171 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) in xgene_mii_phy_read() argument
177 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
178 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
181 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_read()
183 data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); in xgene_mii_phy_read()
184 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
191 netdev_err(p->ndev, "MII_MGMT read failed\n"); in xgene_mii_phy_read()
196 static void xgene_sgmac_reset(struct xgene_enet_pdata *p) in xgene_sgmac_reset() argument
198 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_sgmac_reset()
199 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); in xgene_sgmac_reset()
202 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) in xgene_sgmac_set_mac_addr() argument
205 u8 *dev_addr = p->ndev->dev_addr; in xgene_sgmac_set_mac_addr()
209 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); in xgene_sgmac_set_mac_addr()
211 addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); in xgene_sgmac_set_mac_addr()
213 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); in xgene_sgmac_set_mac_addr()
216 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p) in xgene_enet_link_status() argument
220 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_enet_link_status()
226 static void xgene_sgmac_init(struct xgene_enet_pdata *p) in xgene_sgmac_init() argument
229 u32 offset = p->port_id * 4; in xgene_sgmac_init()
231 xgene_sgmac_reset(p); in xgene_sgmac_init()
234 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000); in xgene_sgmac_init()
235 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); in xgene_sgmac_init()
238 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_sgmac_init()
245 netdev_err(p->ndev, "Auto-negotiation failed\n"); in xgene_sgmac_init()
247 data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); in xgene_sgmac_init()
249 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2); in xgene_sgmac_init()
250 xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE); in xgene_sgmac_init()
252 data = xgene_enet_rd_csr(p, ENET_SPARE_CFG_REG_ADDR); in xgene_sgmac_init()
254 xgene_enet_wr_csr(p, ENET_SPARE_CFG_REG_ADDR, data); in xgene_sgmac_init()
256 xgene_sgmac_set_mac_addr(p); in xgene_sgmac_init()
258 data = xgene_enet_rd_csr(p, DEBUG_REG_ADDR); in xgene_sgmac_init()
260 xgene_enet_wr_csr(p, DEBUG_REG_ADDR, data); in xgene_sgmac_init()
263 data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); in xgene_sgmac_init()
265 xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); in xgene_sgmac_init()
268 data = xgene_enet_rd_csr(p, RSIF_CONFIG_REG_ADDR); in xgene_sgmac_init()
270 xgene_enet_wr_csr(p, RSIF_CONFIG_REG_ADDR, data); in xgene_sgmac_init()
273 xgene_enet_wr_csr(p, RSIF_RAM_DBG_REG0_ADDR, 0); in xgene_sgmac_init()
276 xgene_enet_wr_csr(p, CFG_LINK_AGGR_RESUME_0_ADDR + offset, TX_PORT0); in xgene_sgmac_init()
277 xgene_enet_wr_csr(p, CFG_BYPASS_ADDR, RESUME_TX); in xgene_sgmac_init()
278 xgene_enet_wr_csr(p, SG_RX_DV_GATE_REG_0_ADDR + offset, RESUME_RX0); in xgene_sgmac_init()
281 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) in xgene_sgmac_rxtx() argument
285 data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); in xgene_sgmac_rxtx()
292 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); in xgene_sgmac_rxtx()
295 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_enable() argument
297 xgene_sgmac_rxtx(p, RX_EN, true); in xgene_sgmac_rx_enable()
300 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_enable() argument
302 xgene_sgmac_rxtx(p, TX_EN, true); in xgene_sgmac_tx_enable()
305 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_disable() argument
307 xgene_sgmac_rxtx(p, RX_EN, false); in xgene_sgmac_rx_disable()
310 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_disable() argument
312 xgene_sgmac_rxtx(p, TX_EN, false); in xgene_sgmac_tx_disable()
315 static int xgene_enet_reset(struct xgene_enet_pdata *p) in xgene_enet_reset() argument
317 if (!xgene_ring_mgr_init(p)) in xgene_enet_reset()
320 clk_prepare_enable(p->clk); in xgene_enet_reset()
321 clk_disable_unprepare(p->clk); in xgene_enet_reset()
322 clk_prepare_enable(p->clk); in xgene_enet_reset()
324 xgene_enet_ecc_init(p); in xgene_enet_reset()
325 xgene_enet_config_ring_if_assoc(p); in xgene_enet_reset()
330 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, in xgene_enet_cle_bypass() argument
334 u32 offset = p->port_id * MAC_OFFSET; in xgene_enet_cle_bypass()
337 xgene_enet_wr_csr(p, CLE_BYPASS_REG0_0_ADDR + offset, data); in xgene_enet_cle_bypass()
341 xgene_enet_wr_csr(p, CLE_BYPASS_REG1_0_ADDR + offset, data); in xgene_enet_cle_bypass()
344 static void xgene_enet_shutdown(struct xgene_enet_pdata *p) in xgene_enet_shutdown() argument
346 clk_disable_unprepare(p->clk); in xgene_enet_shutdown()
351 struct xgene_enet_pdata *p = container_of(to_delayed_work(work), in xgene_enet_link_state() local
353 struct net_device *ndev = p->ndev; in xgene_enet_link_state()
356 link = xgene_enet_link_status(p); in xgene_enet_link_state()
360 xgene_sgmac_init(p); in xgene_enet_link_state()
361 xgene_sgmac_rx_enable(p); in xgene_enet_link_state()
362 xgene_sgmac_tx_enable(p); in xgene_enet_link_state()
368 xgene_sgmac_rx_disable(p); in xgene_enet_link_state()
369 xgene_sgmac_tx_disable(p); in xgene_enet_link_state()
376 schedule_delayed_work(&p->link_work, poll_interval); in xgene_enet_link_state()