Lines Matching refs:pdata
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_wr32() local
77 iowrite32(data, pdata->ring_csr_addr + offset); in xgene_enet_ring_wr32()
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_rd32() local
85 *data = ioread32(pdata->ring_csr_addr + offset); in xgene_enet_ring_rd32()
190 struct xgene_enet_pdata *pdata, in xgene_enet_parse_error() argument
193 struct rtnl_link_stats64 *stats = &pdata->stats; in xgene_enet_parse_error()
220 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_csr() argument
223 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_wr_csr()
228 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, in xgene_enet_wr_ring_if() argument
231 void __iomem *addr = pdata->eth_ring_if_addr + offset; in xgene_enet_wr_ring_if()
236 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_diag_csr() argument
239 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_wr_diag_csr()
244 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_mcx_csr() argument
247 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_wr_mcx_csr()
275 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata, in xgene_enet_wr_mcx_mac() argument
280 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_wr_mcx_mac()
281 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; in xgene_enet_wr_mcx_mac()
282 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_wr_mcx_mac()
283 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_wr_mcx_mac()
286 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", in xgene_enet_wr_mcx_mac()
290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() argument
293 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_rd_csr()
298 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_diag_csr() argument
301 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_rd_diag_csr()
306 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_mcx_csr() argument
309 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_rd_mcx_csr()
337 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata, in xgene_enet_rd_mcx_mac() argument
342 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_rd_mcx_mac()
343 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; in xgene_enet_rd_mcx_mac()
344 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_rd_mcx_mac()
345 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_rd_mcx_mac()
348 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", in xgene_enet_rd_mcx_mac()
352 static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id, in xgene_mii_phy_write() argument
361 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
364 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
367 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); in xgene_mii_phy_write()
371 netdev_err(pdata->ndev, "MII_MGMT write failed\n"); in xgene_mii_phy_write()
378 static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata, in xgene_mii_phy_read() argument
387 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
388 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
391 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); in xgene_mii_phy_read()
395 netdev_err(pdata->ndev, "MII_MGMT read failed\n"); in xgene_mii_phy_read()
399 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data); in xgene_mii_phy_read()
400 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
405 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata) in xgene_gmac_set_mac_addr() argument
408 u8 *dev_addr = pdata->ndev->dev_addr; in xgene_gmac_set_mac_addr()
414 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0); in xgene_gmac_set_mac_addr()
415 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1); in xgene_gmac_set_mac_addr()
418 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) in xgene_enet_ecc_init() argument
420 struct net_device *ndev = pdata->ndev; in xgene_enet_ecc_init()
424 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); in xgene_enet_ecc_init()
427 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); in xgene_enet_ecc_init()
438 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata) in xgene_gmac_reset() argument
440 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_gmac_reset()
441 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0); in xgene_gmac_reset()
444 static void xgene_gmac_init(struct xgene_enet_pdata *pdata) in xgene_gmac_init() argument
450 xgene_gmac_reset(pdata); in xgene_gmac_init()
452 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0); in xgene_gmac_init()
453 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2); in xgene_gmac_init()
454 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2); in xgene_gmac_init()
455 xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl); in xgene_gmac_init()
456 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_init()
458 switch (pdata->phy_speed) { in xgene_gmac_init()
476 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_init()
478 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); in xgene_gmac_init()
483 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2); in xgene_gmac_init()
484 xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); in xgene_gmac_init()
486 xgene_gmac_set_mac_addr(pdata); in xgene_gmac_init()
489 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value); in xgene_gmac_init()
491 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value); in xgene_gmac_init()
494 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
496 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); in xgene_gmac_init()
499 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); in xgene_gmac_init()
500 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); in xgene_gmac_init()
503 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); in xgene_gmac_init()
505 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0); in xgene_gmac_init()
506 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2); in xgene_gmac_init()
508 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value); in xgene_gmac_init()
512 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value); in xgene_gmac_init()
514 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); in xgene_gmac_init()
517 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) in xgene_enet_config_ring_if_assoc() argument
521 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
522 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
523 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
524 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
527 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, in xgene_enet_cle_bypass() argument
535 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
538 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); in xgene_enet_cle_bypass()
540 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()
543 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb); in xgene_enet_cle_bypass()
546 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_enable() argument
550 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_rx_enable()
551 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN); in xgene_gmac_rx_enable()
554 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_enable() argument
558 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_tx_enable()
559 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN); in xgene_gmac_tx_enable()
562 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_disable() argument
566 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_rx_disable()
567 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN); in xgene_gmac_rx_disable()
570 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_disable() argument
574 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_tx_disable()
575 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN); in xgene_gmac_tx_disable()
589 static int xgene_enet_reset(struct xgene_enet_pdata *pdata) in xgene_enet_reset() argument
593 if (!xgene_ring_mgr_init(pdata)) in xgene_enet_reset()
596 if (pdata->clk) { in xgene_enet_reset()
597 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
598 clk_disable_unprepare(pdata->clk); in xgene_enet_reset()
599 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
600 xgene_enet_ecc_init(pdata); in xgene_enet_reset()
602 xgene_enet_config_ring_if_assoc(pdata); in xgene_enet_reset()
605 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val); in xgene_enet_reset()
608 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val); in xgene_enet_reset()
613 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) in xgene_gport_shutdown() argument
615 clk_disable_unprepare(pdata->clk); in xgene_gport_shutdown()
620 struct xgene_enet_pdata *pdata = bus->priv; in xgene_enet_mdio_read() local
623 val = xgene_mii_phy_read(pdata, mii_id, regnum); in xgene_enet_mdio_read()
624 netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n", in xgene_enet_mdio_read()
633 struct xgene_enet_pdata *pdata = bus->priv; in xgene_enet_mdio_write() local
635 netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n", in xgene_enet_mdio_write()
637 return xgene_mii_phy_write(pdata, mii_id, regnum, val); in xgene_enet_mdio_write()
642 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_adjust_link() local
643 struct phy_device *phydev = pdata->phy_dev; in xgene_enet_adjust_link()
646 if (pdata->phy_speed != phydev->speed) { in xgene_enet_adjust_link()
647 pdata->phy_speed = phydev->speed; in xgene_enet_adjust_link()
648 xgene_gmac_init(pdata); in xgene_enet_adjust_link()
649 xgene_gmac_rx_enable(pdata); in xgene_enet_adjust_link()
650 xgene_gmac_tx_enable(pdata); in xgene_enet_adjust_link()
654 xgene_gmac_rx_disable(pdata); in xgene_enet_adjust_link()
655 xgene_gmac_tx_disable(pdata); in xgene_enet_adjust_link()
656 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_adjust_link()
663 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_phy_connect() local
666 struct device *dev = &pdata->pdev->dev; in xgene_enet_phy_connect()
674 pdata->phy_dev = of_phy_find_device(phy_np); in xgene_enet_phy_connect()
677 phy_dev = pdata->phy_dev; in xgene_enet_phy_connect()
681 pdata->phy_mode)) { in xgene_enet_phy_connect()
686 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_phy_connect()
695 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata, in xgene_mdiobus_register() argument
698 struct device *dev = &pdata->pdev->dev; in xgene_mdiobus_register()
699 struct net_device *ndev = pdata->ndev; in xgene_mdiobus_register()
745 pdata->phy_dev = phy; in xgene_mdiobus_register()
750 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_config() argument
752 struct net_device *ndev = pdata->ndev; in xgene_enet_mdio_config()
766 mdio_bus->priv = pdata; in xgene_enet_mdio_config()
769 ret = xgene_mdiobus_register(pdata, mdio_bus); in xgene_enet_mdio_config()
775 pdata->mdio_bus = mdio_bus; in xgene_enet_mdio_config()
779 xgene_enet_mdio_remove(pdata); in xgene_enet_mdio_config()
784 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_remove() argument
786 mdiobus_unregister(pdata->mdio_bus); in xgene_enet_mdio_remove()
787 mdiobus_free(pdata->mdio_bus); in xgene_enet_mdio_remove()
788 pdata->mdio_bus = NULL; in xgene_enet_mdio_remove()