497 	unsigned int reg, reg_val;  in xgbe_disable_tx_flow_control()  local
509 		reg_val = XGMAC_IOREAD(pdata, reg);  in xgbe_disable_tx_flow_control()
510 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);  in xgbe_disable_tx_flow_control()
511 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_disable_tx_flow_control()
522 	unsigned int reg, reg_val;  in xgbe_enable_tx_flow_control()  local
534 		reg_val = XGMAC_IOREAD(pdata, reg);  in xgbe_enable_tx_flow_control()
537 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);  in xgbe_enable_tx_flow_control()
539 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);  in xgbe_enable_tx_flow_control()
541 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_enable_tx_flow_control()
1347 	unsigned int mask, reg, reg_val;  in xgbe_config_dcb_pfc()  local
1364 		reg_val = XGMAC_IOREAD(pdata, reg);  in xgbe_config_dcb_pfc()
1366 		reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));  in xgbe_config_dcb_pfc()
1367 		reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));  in xgbe_config_dcb_pfc()
1369 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_config_dcb_pfc()
2056 	unsigned int i, j, reg, reg_val;  in xgbe_config_queue_mapping()  local
2087 	reg_val = 0;  in xgbe_config_queue_mapping()
2102 		reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));  in xgbe_config_queue_mapping()
2107 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_config_queue_mapping()
2109 		reg_val = 0;  in xgbe_config_queue_mapping()
2114 	reg_val = 0;  in xgbe_config_queue_mapping()
2116 		reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));  in xgbe_config_queue_mapping()
2121 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_config_queue_mapping()
2124 		reg_val = 0;  in xgbe_config_queue_mapping()
2650 	unsigned int reg_val, i;  in xgbe_enable_rx()  local
2662 	reg_val = 0;  in xgbe_enable_rx()
2664 		reg_val |= (0x02 << (i << 1));  in xgbe_enable_rx()
2665 	XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);  in xgbe_enable_rx()