Lines Matching refs:AM2150_MACE_BASE
192 #define AM2150_MACE_BASE 0x10 macro
493 data = inb(ioaddr + AM2150_MACE_BASE + reg); in mace_read()
498 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); in mace_read()
520 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); in mace_write()
525 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); in mace_write()
810 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_close()
872 ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_start_xmit()
905 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); in mace_start_xmit()
941 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), in mace_interrupt()
942 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)); in mace_interrupt()
954 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); in mace_interrupt()
969 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); in mace_interrupt()
976 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); in mace_interrupt()
981 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & in mace_interrupt()