Lines Matching refs:u32
126 u32 control; /* PHY device operation control register */
127 u32 status; /* PHY device operation status register */
128 u32 phy_id1; /* Bits 31:16 of PHY identifier */
129 u32 phy_id2; /* Bits 15:0 of PHY identifier */
130 u32 auto_negotiation_advertisement; /* Auto-negotiation
134 u32 remote_partner_base_page_ability;
136 u32 reg6;
137 u32 reg7;
138 u32 reg8;
139 u32 reg9;
140 u32 rega;
141 u32 regb;
142 u32 regc;
143 u32 regd;
144 u32 rege;
145 u32 regf;
146 u32 reg10;
147 u32 reg11;
148 u32 reg12;
149 u32 reg13;
150 u32 reg14;
151 u32 reg15;
152 u32 reg16;
153 u32 reg17;
154 u32 reg18;
155 u32 reg19;
156 u32 reg1a;
157 u32 reg1b;
158 u32 reg1c;
159 u32 reg1d;
160 u32 reg1e;
161 u32 reg1f;
173 u32 megacore_revision;
177 u32 scratch_pad;
181 u32 command_config;
185 u32 mac_addr_0;
189 u32 mac_addr_1;
191 u32 frm_length;
195 u32 pause_quanta;
197 u32 rx_section_empty;
199 u32 rx_section_full;
201 u32 tx_section_empty;
203 u32 tx_section_full;
205 u32 rx_almost_empty;
207 u32 rx_almost_full;
209 u32 tx_almost_empty;
211 u32 tx_almost_full;
213 u32 mdio_phy0_addr;
215 u32 mdio_phy1_addr;
218 u32 holdoff_quant;
221 u32 reserved1[5];
224 u32 tx_ipg_length;
229 u32 mac_id_1;
230 u32 mac_id_2;
233 u32 frames_transmitted_ok;
235 u32 frames_received_ok;
237 u32 frames_check_sequence_errors;
239 u32 alignment_errors;
243 u32 octets_transmitted_ok;
245 u32 octets_received_ok;
250 u32 tx_pause_mac_ctrl_frames;
252 u32 rx_pause_mac_ctrl_frames;
257 u32 if_in_errors;
259 u32 if_out_errors;
261 u32 if_in_ucast_pkts;
263 u32 if_in_multicast_pkts;
265 u32 if_in_broadcast_pkts;
266 u32 if_out_discards;
268 u32 if_out_ucast_pkts;
272 u32 if_out_multicast_pkts;
273 u32 if_out_broadcast_pkts;
280 u32 ether_stats_drop_events;
282 u32 ether_stats_octets;
284 u32 ether_stats_pkts;
286 u32 ether_stats_undersize_pkts;
290 u32 ether_stats_oversize_pkts;
292 u32 ether_stats_pkts_64_octets;
294 u32 ether_stats_pkts_65to127_octets;
296 u32 ether_stats_pkts_128to255_octets;
298 u32 ether_stats_pkts_256to511_octets;
300 u32 ether_stats_pkts_512to1023_octets;
302 u32 ether_stats_pkts_1024to1518_octets;
307 u32 ether_stats_pkts_1519tox_octets;
309 u32 ether_stats_jabbers;
311 u32 ether_stats_fragments;
313 u32 reserved2;
316 u32 tx_cmd_stat;
317 u32 rx_cmd_stat;
320 u32 msb_octets_transmitted_ok;
321 u32 msb_octets_received_ok;
322 u32 msb_ether_stats_octets;
324 u32 reserved3;
329 u32 hash_table[64];
338 u32 supp_mac_addr_0_0;
339 u32 supp_mac_addr_0_1;
340 u32 supp_mac_addr_1_0;
341 u32 supp_mac_addr_1_1;
342 u32 supp_mac_addr_2_0;
343 u32 supp_mac_addr_2_1;
344 u32 supp_mac_addr_3_0;
345 u32 supp_mac_addr_3_1;
347 u32 reserved4[8];
350 u32 tx_period;
351 u32 tx_adjust_fns;
352 u32 tx_adjust_ns;
353 u32 rx_period;
354 u32 rx_adjust_fns;
355 u32 rx_adjust_ns;
357 u32 reserved5[42];
375 u32 len;
396 u32 (*tx_completions)(struct altera_tse_private *);
398 u32 (*get_rx_status)(struct altera_tse_private *);
415 u32 revision;
428 u32 rx_cons;
429 u32 rx_prod;
430 u32 rx_ring_size;
431 u32 rx_dma_buf_sz;
435 u32 tx_prod;
436 u32 tx_cons;
437 u32 tx_ring_size;
440 u32 tx_irq;
441 u32 rx_irq;
444 u32 tx_fifo_depth;
445 u32 rx_fifo_depth;
446 u32 max_mtu;
449 u32 hash_filter;
450 u32 added_unicast;
453 u32 txdescmem;
454 u32 rxdescmem;
457 u32 txctrlreg;
458 u32 rxctrlreg;
483 u32 msg_enable;
493 u32 csrrd32(void __iomem *mac, size_t offs) in csrrd32()
514 void csrwr32(u32 val, void __iomem *mac, size_t offs) in csrwr32()