755 	writel(csr, &adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
757 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
760 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
774 	       &adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
775 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
778 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
1541 	struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;  in et131x_config_rx_dma_regs()
2120 		writel(0, &adapter->regs->rxdma.max_pkt_time);  in et131x_set_rx_dma_timer()
2121 		writel(1, &adapter->regs->rxdma.num_pkt_done);  in et131x_set_rx_dma_timer()
2129 	struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;  in nic_return_rfd()
2234 	writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);  in nic_rx_pkts()
2939 	regs_buff[num++] = readl(&aregs->rxdma.csr);  in et131x_get_regs()
2940 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);  in et131x_get_regs()
2941 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);  in et131x_get_regs()
2942 	regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);  in et131x_get_regs()
2943 	regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);  in et131x_get_regs()
2944 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);  in et131x_get_regs()
2945 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);  in et131x_get_regs()
2946 	regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);  in et131x_get_regs()
2947 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);  in et131x_get_regs()
2948 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);  in et131x_get_regs()
2949 	regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);  in et131x_get_regs()
2950 	regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);  in et131x_get_regs()
2951 	regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);  in et131x_get_regs()
2952 	regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);  in et131x_get_regs()
2953 	regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);  in et131x_get_regs()
2954 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);  in et131x_get_regs()
2955 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);  in et131x_get_regs()
2956 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);  in et131x_get_regs()
2957 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);  in et131x_get_regs()
2958 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);  in et131x_get_regs()
2959 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);  in et131x_get_regs()
2960 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);  in et131x_get_regs()
2961 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);  in et131x_get_regs()
2962 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);  in et131x_get_regs()
2963 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);  in et131x_get_regs()
2964 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);  in et131x_get_regs()
2965 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);  in et131x_get_regs()
2966 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);  in et131x_get_regs()
2967 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);  in et131x_get_regs()