298 static inline void flexcan_write(u32 val, void __iomem *addr)  in flexcan_write()  function
308 static inline void flexcan_write(u32 val, void __iomem *addr)  in flexcan_write()  function
345 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_enable()
364 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_disable()
383 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_freeze()
402 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_unfreeze()
418 	flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);  in flexcan_chip_softreset()
490 		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);  in flexcan_start_xmit()
494 		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);  in flexcan_start_xmit()
499 	flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);  in flexcan_start_xmit()
500 	flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);  in flexcan_start_xmit()
505 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
507 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
647 	flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);  in flexcan_read_fifo()
706 		flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);  in flexcan_poll()
707 		flexcan_write(priv->reg_ctrl_default, &regs->ctrl);  in flexcan_poll()
725 		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);  in flexcan_irq()
741 		flexcan_write(FLEXCAN_IFLAG_DEFAULT &  in flexcan_irq()
743 		flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,  in flexcan_irq()
750 		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);  in flexcan_irq()
761 		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_irq()
763 		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);  in flexcan_irq()
801 	flexcan_write(reg, &regs->ctrl);  in flexcan_set_bittiming()
852 	flexcan_write(reg_mcr, &regs->mcr);  in flexcan_chip_start()
884 	flexcan_write(reg_ctrl, &regs->ctrl);  in flexcan_chip_start()
888 		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,  in flexcan_chip_start()
893 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
897 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
901 	flexcan_write(0x0, &regs->rxgmask);  in flexcan_chip_start()
902 	flexcan_write(0x0, &regs->rx14mask);  in flexcan_chip_start()
903 	flexcan_write(0x0, &regs->rx15mask);  in flexcan_chip_start()
906 		flexcan_write(0x0, &regs->rxfgmask);  in flexcan_chip_start()
923 		flexcan_write(reg_crl2, &regs->crl2);  in flexcan_chip_start()
927 		flexcan_write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
930 		flexcan_write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
945 	flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);  in flexcan_chip_start()
976 	flexcan_write(0, &regs->imask1);  in flexcan_chip_stop()
977 	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,  in flexcan_chip_stop()
1097 	flexcan_write(reg, &regs->ctrl);  in register_flexcandev()
1107 	flexcan_write(reg, &regs->mcr);  in register_flexcandev()