Lines Matching refs:u8
22 u8 ctrl0;
23 u8 ctrl1;
24 u8 id[4];
25 u8 config;
26 u8 data[8];
27 u8 dontuse; /* padding */
34 u8 control; /* Control Register */
35 u8 status; /* Status Register */
36 u8 cpu_interface; /* CPU Interface Register */
37 u8 dontuse1;
38 u8 high_speed_read[2]; /* High Speed Read */
39 u8 global_mask_std[2]; /* Standard Global Mask */
40 u8 global_mask_ext[4]; /* Extended Global Mask */
41 u8 msg15_mask[4]; /* Message 15 Mask */
42 u8 dontuse2[15];
43 u8 clkout; /* Clock Out Register */
44 u8 dontuse3[15];
45 u8 bus_config; /* Bus Configuration Register */
46 u8 dontuse4[15];
47 u8 bit_timing_0; /* Bit Timing Register byte 0 */
48 u8 dontuse5[15];
49 u8 bit_timing_1; /* Bit Timing Register byte 1 */
50 u8 dontuse6[15];
51 u8 interrupt; /* Interrupt Register */
52 u8 dontuse7[15];
53 u8 rx_error_counter; /* Receive Error Counter */
54 u8 dontuse8[15];
55 u8 tx_error_counter; /* Transmit Error Counter */
56 u8 dontuse9[31];
57 u8 p1_conf;
58 u8 dontuse10[15];
59 u8 p2_conf;
60 u8 dontuse11[15];
61 u8 p1_in;
62 u8 dontuse12[15];
63 u8 p2_in;
64 u8 dontuse13[15];
65 u8 p1_out;
66 u8 dontuse14[15];
67 u8 p2_out;
68 u8 dontuse15[15];
69 u8 serial_reset_addr;
180 u8 (*read_reg)(const struct cc770_priv *priv, int reg);
181 void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val);
192 u8 control_normal_mode; /* Control register for normal mode */
193 u8 cpu_interface; /* CPU interface register */
194 u8 clkout; /* Clock out register */
195 u8 bus_config; /* Bus conffiguration register */