289 	u32 lut_base;  in fsl_qspi_init_lut()  local
300 	lut_base = SEQID_QUAD_READ * 4;  in fsl_qspi_init_lut()
314 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
316 			base + QUADSPI_LUT(lut_base + 1));  in fsl_qspi_init_lut()
319 	lut_base = SEQID_WREN * 4;  in fsl_qspi_init_lut()
320 	writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
323 	lut_base = SEQID_PP * 4;  in fsl_qspi_init_lut()
335 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
336 	writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));  in fsl_qspi_init_lut()
339 	lut_base = SEQID_RDSR * 4;  in fsl_qspi_init_lut()
341 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
344 	lut_base = SEQID_SE * 4;  in fsl_qspi_init_lut()
356 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
359 	lut_base = SEQID_CHIP_ERASE * 4;  in fsl_qspi_init_lut()
361 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
364 	lut_base = SEQID_RDID * 4;  in fsl_qspi_init_lut()
366 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
369 	lut_base = SEQID_WRSR * 4;  in fsl_qspi_init_lut()
371 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
374 	lut_base = SEQID_RDCR * 4;  in fsl_qspi_init_lut()
376 			base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
379 	lut_base = SEQID_WRDI * 4;  in fsl_qspi_init_lut()
380 	writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
383 	lut_base = SEQID_EN4B * 4;  in fsl_qspi_init_lut()
384 	writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
387 	lut_base = SEQID_BRWR * 4;  in fsl_qspi_init_lut()
388 	writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()