313 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
320 	writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
334 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
340 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),  in fsl_qspi_init_lut()
355 	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),  in fsl_qspi_init_lut()
360 	writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),  in fsl_qspi_init_lut()
365 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),  in fsl_qspi_init_lut()
370 	writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),  in fsl_qspi_init_lut()
375 	writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),  in fsl_qspi_init_lut()
380 	writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
384 	writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()
388 	writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));  in fsl_qspi_init_lut()