129 #define nand_writel(info, off, val)	\  macro
383 	nand_writel(info, NDTR0CS0, ndtr0);  in pxa3xx_nand_set_timing()
384 	nand_writel(info, NDTR1CS0, ndtr1);  in pxa3xx_nand_set_timing()
421 			nand_writel(info, NDECCCTRL, 0x1);  in pxa3xx_nand_start()
425 			nand_writel(info, NDECCCTRL, 0x0);  in pxa3xx_nand_start()
441 	nand_writel(info, NDCR, 0);  in pxa3xx_nand_start()
442 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_start()
443 	nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_start()
460 		nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_stop()
463 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_stop()
472 	nand_writel(info, NDCR, ndcr & ~int_mask);  in enable_int()
480 	nand_writel(info, NDCR, ndcr | int_mask);  in disable_int()
601 	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);  in pxa3xx_nand_data_dma_irq()
615 	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);  in pxa3xx_nand_irq_thread()
681 		nand_writel(info, NDSR, NDSR_WRCMDREQ);  in pxa3xx_nand_irq()
693 		nand_writel(info, NDCB0, info->ndcb0);  in pxa3xx_nand_irq()
694 		nand_writel(info, NDCB0, info->ndcb1);  in pxa3xx_nand_irq()
695 		nand_writel(info, NDCB0, info->ndcb2);  in pxa3xx_nand_irq()
699 			nand_writel(info, NDCB0, info->ndcb3);  in pxa3xx_nand_irq()
703 	nand_writel(info, NDSR, status);  in pxa3xx_nand_irq()
985 		nand_writel(info, NDTR0CS0, info->ndtr0cs0);  in nand_cmdfunc()
986 		nand_writel(info, NDTR1CS0, info->ndtr1cs0);  in nand_cmdfunc()
1033 		nand_writel(info, NDTR0CS0, info->ndtr0cs0);  in nand_cmdfunc_extended()
1034 		nand_writel(info, NDTR1CS0, info->ndtr1cs0);  in nand_cmdfunc_extended()
1542 		nand_writel(info, NDECCCTRL, 0x0);  in pxa3xx_nand_scan()
1916 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_resume()