Lines Matching refs:info
129 #define nand_writel(info, off, val) \ argument
130 writel_relaxed((val), (info)->mmio_base + (off))
132 #define nand_readl(info, off) \ argument
133 readl_relaxed((info)->mmio_base + (off))
366 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_timing() local
367 unsigned long nand_clk = clk_get_rate(info->clk); in pxa3xx_nand_set_timing()
381 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_timing()
382 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_timing()
383 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_timing()
384 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_timing()
392 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info, in pxa3xx_set_datasize() argument
395 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; in pxa3xx_set_datasize()
397 info->data_size = mtd->writesize; in pxa3xx_set_datasize()
401 info->oob_size = info->spare_size; in pxa3xx_set_datasize()
402 if (!info->use_ecc) in pxa3xx_set_datasize()
403 info->oob_size += info->ecc_size; in pxa3xx_set_datasize()
412 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) in pxa3xx_nand_start() argument
416 ndcr = info->reg_ndcr; in pxa3xx_nand_start()
418 if (info->use_ecc) { in pxa3xx_nand_start()
420 if (info->ecc_bch) in pxa3xx_nand_start()
421 nand_writel(info, NDECCCTRL, 0x1); in pxa3xx_nand_start()
424 if (info->ecc_bch) in pxa3xx_nand_start()
425 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_start()
428 if (info->use_dma) in pxa3xx_nand_start()
433 if (info->use_spare) in pxa3xx_nand_start()
441 nand_writel(info, NDCR, 0); in pxa3xx_nand_start()
442 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_start()
443 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_start()
446 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) in pxa3xx_nand_stop() argument
452 ndcr = nand_readl(info, NDCR); in pxa3xx_nand_stop()
454 ndcr = nand_readl(info, NDCR); in pxa3xx_nand_stop()
460 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_stop()
463 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_stop()
467 enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in enable_int() argument
471 ndcr = nand_readl(info, NDCR); in enable_int()
472 nand_writel(info, NDCR, ndcr & ~int_mask); in enable_int()
475 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in disable_int() argument
479 ndcr = nand_readl(info, NDCR); in disable_int()
480 nand_writel(info, NDCR, ndcr | int_mask); in disable_int()
483 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) in drain_fifo() argument
485 if (info->ecc_bch) { in drain_fifo()
497 __raw_readsl(info->mmio_base + NDDB, data, 8); in drain_fifo()
500 !(nand_readl(info, NDSR) & NDSR_RDDREQ); in drain_fifo()
503 dev_err(&info->pdev->dev, in drain_fifo()
516 __raw_readsl(info->mmio_base + NDDB, data, len); in drain_fifo()
519 static void handle_data_pio(struct pxa3xx_nand_info *info) in handle_data_pio() argument
521 unsigned int do_bytes = min(info->data_size, info->chunk_size); in handle_data_pio()
523 switch (info->state) { in handle_data_pio()
525 __raw_writesl(info->mmio_base + NDDB, in handle_data_pio()
526 info->data_buff + info->data_buff_pos, in handle_data_pio()
529 if (info->oob_size > 0) in handle_data_pio()
530 __raw_writesl(info->mmio_base + NDDB, in handle_data_pio()
531 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
532 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
535 drain_fifo(info, in handle_data_pio()
536 info->data_buff + info->data_buff_pos, in handle_data_pio()
539 if (info->oob_size > 0) in handle_data_pio()
540 drain_fifo(info, in handle_data_pio()
541 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
542 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
545 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in handle_data_pio()
546 info->state); in handle_data_pio()
551 info->data_buff_pos += do_bytes; in handle_data_pio()
552 info->oob_buff_pos += info->oob_size; in handle_data_pio()
553 info->data_size -= do_bytes; in handle_data_pio()
557 static void start_data_dma(struct pxa3xx_nand_info *info) in start_data_dma() argument
559 struct pxa_dma_desc *desc = info->data_desc; in start_data_dma()
560 int dma_len = ALIGN(info->data_size + info->oob_size, 32); in start_data_dma()
565 switch (info->state) { in start_data_dma()
567 desc->dsadr = info->data_buff_phys; in start_data_dma()
568 desc->dtadr = info->mmio_phys + NDDB; in start_data_dma()
572 desc->dtadr = info->data_buff_phys; in start_data_dma()
573 desc->dsadr = info->mmio_phys + NDDB; in start_data_dma()
577 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in start_data_dma()
578 info->state); in start_data_dma()
582 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; in start_data_dma()
583 DDADR(info->data_dma_ch) = info->data_desc_addr; in start_data_dma()
584 DCSR(info->data_dma_ch) |= DCSR_RUN; in start_data_dma()
589 struct pxa3xx_nand_info *info = data; in pxa3xx_nand_data_dma_irq() local
596 info->retcode = ERR_DMABUSERR; in pxa3xx_nand_data_dma_irq()
599 info->state = STATE_DMA_DONE; in pxa3xx_nand_data_dma_irq()
600 enable_int(info, NDCR_INT_MASK); in pxa3xx_nand_data_dma_irq()
601 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_data_dma_irq()
604 static void start_data_dma(struct pxa3xx_nand_info *info) in start_data_dma() argument
610 struct pxa3xx_nand_info *info = data; in pxa3xx_nand_irq_thread() local
612 handle_data_pio(info); in pxa3xx_nand_irq_thread()
614 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq_thread()
615 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_irq_thread()
622 struct pxa3xx_nand_info *info = devid; in pxa3xx_nand_irq() local
627 if (info->cs == 0) { in pxa3xx_nand_irq()
635 status = nand_readl(info, NDSR); in pxa3xx_nand_irq()
638 info->retcode = ERR_UNCORERR; in pxa3xx_nand_irq()
640 info->retcode = ERR_CORERR; in pxa3xx_nand_irq()
641 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && in pxa3xx_nand_irq()
642 info->ecc_bch) in pxa3xx_nand_irq()
643 info->ecc_err_cnt = NDSR_ERR_CNT(status); in pxa3xx_nand_irq()
645 info->ecc_err_cnt = 1; in pxa3xx_nand_irq()
652 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_irq()
653 info->max_bitflips, in pxa3xx_nand_irq()
654 info->ecc_err_cnt); in pxa3xx_nand_irq()
658 if (info->use_dma) { in pxa3xx_nand_irq()
659 disable_int(info, NDCR_INT_MASK); in pxa3xx_nand_irq()
660 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
662 start_data_dma(info); in pxa3xx_nand_irq()
665 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
672 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq()
676 info->state = STATE_READY; in pxa3xx_nand_irq()
681 nand_writel(info, NDSR, NDSR_WRCMDREQ); in pxa3xx_nand_irq()
683 info->state = STATE_CMD_HANDLE; in pxa3xx_nand_irq()
693 nand_writel(info, NDCB0, info->ndcb0); in pxa3xx_nand_irq()
694 nand_writel(info, NDCB0, info->ndcb1); in pxa3xx_nand_irq()
695 nand_writel(info, NDCB0, info->ndcb2); in pxa3xx_nand_irq()
698 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_irq()
699 nand_writel(info, NDCB0, info->ndcb3); in pxa3xx_nand_irq()
703 nand_writel(info, NDSR, status); in pxa3xx_nand_irq()
705 complete(&info->cmd_complete); in pxa3xx_nand_irq()
707 complete(&info->dev_ready); in pxa3xx_nand_irq()
720 static void set_command_address(struct pxa3xx_nand_info *info, in set_command_address() argument
725 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) in set_command_address()
728 info->ndcb2 = 0; in set_command_address()
730 info->ndcb1 = ((page_addr & 0xFFFF) << 16) in set_command_address()
734 info->ndcb2 = (page_addr & 0xFF0000) >> 16; in set_command_address()
736 info->ndcb2 = 0; in set_command_address()
740 static void prepare_start_command(struct pxa3xx_nand_info *info, int command) in prepare_start_command() argument
742 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
746 info->buf_start = 0; in prepare_start_command()
747 info->buf_count = 0; in prepare_start_command()
748 info->oob_size = 0; in prepare_start_command()
749 info->data_buff_pos = 0; in prepare_start_command()
750 info->oob_buff_pos = 0; in prepare_start_command()
751 info->use_ecc = 0; in prepare_start_command()
752 info->use_spare = 1; in prepare_start_command()
753 info->retcode = ERR_NONE; in prepare_start_command()
754 info->ecc_err_cnt = 0; in prepare_start_command()
755 info->ndcb3 = 0; in prepare_start_command()
756 info->need_wait = 0; in prepare_start_command()
761 info->use_ecc = 1; in prepare_start_command()
763 pxa3xx_set_datasize(info, mtd); in prepare_start_command()
766 info->use_spare = 0; in prepare_start_command()
769 info->ndcb1 = 0; in prepare_start_command()
770 info->ndcb2 = 0; in prepare_start_command()
782 info->buf_count = mtd->writesize + mtd->oobsize; in prepare_start_command()
783 memset(info->data_buff, 0xFF, info->buf_count); in prepare_start_command()
788 static int prepare_set_command(struct pxa3xx_nand_info *info, int command, in prepare_set_command() argument
795 host = info->host[info->cs]; in prepare_set_command()
800 if (info->cs != 0) in prepare_set_command()
801 info->ndcb0 = NDCB0_CSEL; in prepare_set_command()
803 info->ndcb0 = 0; in prepare_set_command()
814 info->buf_start = column; in prepare_set_command()
815 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
820 info->buf_start += mtd->writesize; in prepare_set_command()
828 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); in prepare_set_command()
830 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) in prepare_set_command()
833 info->ndcb3 = info->chunk_size + in prepare_set_command()
834 info->oob_size; in prepare_set_command()
837 set_command_address(info, mtd->writesize, column, page_addr); in prepare_set_command()
842 info->buf_start = column; in prepare_set_command()
843 set_command_address(info, mtd->writesize, 0, page_addr); in prepare_set_command()
850 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
855 info->data_size = 0; in prepare_set_command()
861 if (is_buf_blank(info->data_buff, in prepare_set_command()
874 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
877 info->ndcb3 = info->chunk_size + in prepare_set_command()
878 info->oob_size; in prepare_set_command()
884 if (info->data_size == 0) { in prepare_set_command()
885 info->ndcb0 = NDCB0_CMD_TYPE(0x1) in prepare_set_command()
888 info->ndcb1 = 0; in prepare_set_command()
889 info->ndcb2 = 0; in prepare_set_command()
890 info->ndcb3 = 0; in prepare_set_command()
893 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
904 info->buf_count = 256; in prepare_set_command()
905 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
909 info->ndcb1 = (column & 0xFF); in prepare_set_command()
910 info->ndcb3 = 256; in prepare_set_command()
911 info->data_size = 256; in prepare_set_command()
915 info->buf_count = host->read_id_bytes; in prepare_set_command()
916 info->ndcb0 |= NDCB0_CMD_TYPE(3) in prepare_set_command()
919 info->ndcb1 = (column & 0xFF); in prepare_set_command()
921 info->data_size = 8; in prepare_set_command()
924 info->buf_count = 1; in prepare_set_command()
925 info->ndcb0 |= NDCB0_CMD_TYPE(4) in prepare_set_command()
929 info->data_size = 8; in prepare_set_command()
933 info->ndcb0 |= NDCB0_CMD_TYPE(2) in prepare_set_command()
939 info->ndcb1 = page_addr; in prepare_set_command()
940 info->ndcb2 = 0; in prepare_set_command()
944 info->ndcb0 |= NDCB0_CMD_TYPE(5) in prepare_set_command()
955 dev_err(&info->pdev->dev, "non-supported command %x\n", in prepare_set_command()
967 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc() local
975 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc()
983 if (info->cs != host->cs) { in nand_cmdfunc()
984 info->cs = host->cs; in nand_cmdfunc()
985 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
986 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc()
989 prepare_start_command(info, command); in nand_cmdfunc()
991 info->state = STATE_PREPARED; in nand_cmdfunc()
992 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); in nand_cmdfunc()
995 init_completion(&info->cmd_complete); in nand_cmdfunc()
996 init_completion(&info->dev_ready); in nand_cmdfunc()
997 info->need_wait = 1; in nand_cmdfunc()
998 pxa3xx_nand_start(info); in nand_cmdfunc()
1000 if (!wait_for_completion_timeout(&info->cmd_complete, in nand_cmdfunc()
1002 dev_err(&info->pdev->dev, "Wait time out!!!\n"); in nand_cmdfunc()
1004 pxa3xx_nand_stop(info); in nand_cmdfunc()
1007 info->state = STATE_IDLE; in nand_cmdfunc()
1015 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc_extended() local
1023 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc_extended()
1031 if (info->cs != host->cs) { in nand_cmdfunc_extended()
1032 info->cs = host->cs; in nand_cmdfunc_extended()
1033 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
1034 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc_extended()
1054 prepare_start_command(info, command); in nand_cmdfunc_extended()
1064 info->need_wait = 1; in nand_cmdfunc_extended()
1065 init_completion(&info->dev_ready); in nand_cmdfunc_extended()
1067 info->state = STATE_PREPARED; in nand_cmdfunc_extended()
1068 exec_cmd = prepare_set_command(info, command, ext_cmd_type, in nand_cmdfunc_extended()
1071 info->need_wait = 0; in nand_cmdfunc_extended()
1072 complete(&info->dev_ready); in nand_cmdfunc_extended()
1076 init_completion(&info->cmd_complete); in nand_cmdfunc_extended()
1077 pxa3xx_nand_start(info); in nand_cmdfunc_extended()
1079 if (!wait_for_completion_timeout(&info->cmd_complete, in nand_cmdfunc_extended()
1081 dev_err(&info->pdev->dev, "Wait time out!!!\n"); in nand_cmdfunc_extended()
1083 pxa3xx_nand_stop(info); in nand_cmdfunc_extended()
1088 if (info->data_size == 0 && command != NAND_CMD_PAGEPROG) in nand_cmdfunc_extended()
1095 if (info->data_size == 0 && in nand_cmdfunc_extended()
1102 if (info->data_size == info->chunk_size) in nand_cmdfunc_extended()
1112 info->data_size == 0) { in nand_cmdfunc_extended()
1117 info->state = STATE_IDLE; in nand_cmdfunc_extended()
1134 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_hwecc() local
1139 if (info->retcode == ERR_CORERR && info->use_ecc) { in pxa3xx_nand_read_page_hwecc()
1140 mtd->ecc_stats.corrected += info->ecc_err_cnt; in pxa3xx_nand_read_page_hwecc()
1142 } else if (info->retcode == ERR_UNCORERR) { in pxa3xx_nand_read_page_hwecc()
1149 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1154 return info->max_bitflips; in pxa3xx_nand_read_page_hwecc()
1160 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_byte() local
1163 if (info->buf_start < info->buf_count) in pxa3xx_nand_read_byte()
1165 retval = info->data_buff[info->buf_start++]; in pxa3xx_nand_read_byte()
1173 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_word() local
1176 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { in pxa3xx_nand_read_word()
1177 retval = *((u16 *)(info->data_buff+info->buf_start)); in pxa3xx_nand_read_word()
1178 info->buf_start += 2; in pxa3xx_nand_read_word()
1186 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_buf() local
1187 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_read_buf()
1189 memcpy(buf, info->data_buff + info->buf_start, real_len); in pxa3xx_nand_read_buf()
1190 info->buf_start += real_len; in pxa3xx_nand_read_buf()
1197 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_write_buf() local
1198 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_write_buf()
1200 memcpy(info->data_buff + info->buf_start, buf, real_len); in pxa3xx_nand_write_buf()
1201 info->buf_start += real_len; in pxa3xx_nand_write_buf()
1212 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_waitfunc() local
1214 if (info->need_wait) { in pxa3xx_nand_waitfunc()
1215 info->need_wait = 0; in pxa3xx_nand_waitfunc()
1216 if (!wait_for_completion_timeout(&info->dev_ready, in pxa3xx_nand_waitfunc()
1218 dev_err(&info->pdev->dev, "Ready time out!!!\n"); in pxa3xx_nand_waitfunc()
1225 if (info->retcode == ERR_NONE) in pxa3xx_nand_waitfunc()
1234 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, in pxa3xx_nand_config_flash() argument
1237 struct platform_device *pdev = info->pdev; in pxa3xx_nand_config_flash()
1239 struct pxa3xx_nand_host *host = info->host[info->cs]; in pxa3xx_nand_config_flash()
1273 info->reg_ndcr = ndcr; in pxa3xx_nand_config_flash()
1279 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) in pxa3xx_nand_detect_config() argument
1285 struct pxa3xx_nand_host *host = info->host[0]; in pxa3xx_nand_detect_config()
1286 uint32_t ndcr = nand_readl(info, NDCR); in pxa3xx_nand_detect_config()
1290 info->chunk_size = 2048; in pxa3xx_nand_detect_config()
1293 info->chunk_size = 512; in pxa3xx_nand_detect_config()
1298 info->reg_ndcr = ndcr & ~NDCR_INT_MASK; in pxa3xx_nand_detect_config()
1299 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
1300 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); in pxa3xx_nand_detect_config()
1305 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_init_buff() argument
1307 struct platform_device *pdev = info->pdev; in pxa3xx_nand_init_buff()
1308 int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc); in pxa3xx_nand_init_buff()
1311 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1312 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1317 info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size, in pxa3xx_nand_init_buff()
1318 &info->data_buff_phys, GFP_KERNEL); in pxa3xx_nand_init_buff()
1319 if (info->data_buff == NULL) { in pxa3xx_nand_init_buff()
1324 info->data_desc = (void *)info->data_buff + data_desc_offset; in pxa3xx_nand_init_buff()
1325 info->data_desc_addr = info->data_buff_phys + data_desc_offset; in pxa3xx_nand_init_buff()
1327 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, in pxa3xx_nand_init_buff()
1328 pxa3xx_nand_data_dma_irq, info); in pxa3xx_nand_init_buff()
1329 if (info->data_dma_ch < 0) { in pxa3xx_nand_init_buff()
1331 dma_free_coherent(&pdev->dev, info->buf_size, in pxa3xx_nand_init_buff()
1332 info->data_buff, info->data_buff_phys); in pxa3xx_nand_init_buff()
1333 return info->data_dma_ch; in pxa3xx_nand_init_buff()
1340 info->use_dma = 1; in pxa3xx_nand_init_buff()
1344 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_free_buff() argument
1346 struct platform_device *pdev = info->pdev; in pxa3xx_nand_free_buff()
1347 if (info->use_dma) { in pxa3xx_nand_free_buff()
1348 pxa_free_dma(info->data_dma_ch); in pxa3xx_nand_free_buff()
1349 dma_free_coherent(&pdev->dev, info->buf_size, in pxa3xx_nand_free_buff()
1350 info->data_buff, info->data_buff_phys); in pxa3xx_nand_free_buff()
1352 kfree(info->data_buff); in pxa3xx_nand_free_buff()
1356 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_init_buff() argument
1358 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1359 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1364 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_free_buff() argument
1366 kfree(info->data_buff); in pxa3xx_nand_free_buff()
1370 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) in pxa3xx_nand_sensing() argument
1376 mtd = info->host[info->cs]->mtd; in pxa3xx_nand_sensing()
1380 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); in pxa3xx_nand_sensing()
1392 static int pxa_ecc_init(struct pxa3xx_nand_info *info, in pxa_ecc_init() argument
1397 info->chunk_size = 2048; in pxa_ecc_init()
1398 info->spare_size = 40; in pxa_ecc_init()
1399 info->ecc_size = 24; in pxa_ecc_init()
1405 info->chunk_size = 512; in pxa_ecc_init()
1406 info->spare_size = 8; in pxa_ecc_init()
1407 info->ecc_size = 8; in pxa_ecc_init()
1417 info->ecc_bch = 1; in pxa_ecc_init()
1418 info->chunk_size = 2048; in pxa_ecc_init()
1419 info->spare_size = 32; in pxa_ecc_init()
1420 info->ecc_size = 32; in pxa_ecc_init()
1422 ecc->size = info->chunk_size; in pxa_ecc_init()
1427 info->ecc_bch = 1; in pxa_ecc_init()
1428 info->chunk_size = 2048; in pxa_ecc_init()
1429 info->spare_size = 32; in pxa_ecc_init()
1430 info->ecc_size = 32; in pxa_ecc_init()
1432 ecc->size = info->chunk_size; in pxa_ecc_init()
1441 info->ecc_bch = 1; in pxa_ecc_init()
1442 info->chunk_size = 1024; in pxa_ecc_init()
1443 info->spare_size = 0; in pxa_ecc_init()
1444 info->ecc_size = 32; in pxa_ecc_init()
1446 ecc->size = info->chunk_size; in pxa_ecc_init()
1450 dev_err(&info->pdev->dev, in pxa_ecc_init()
1456 dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n", in pxa_ecc_init()
1464 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_scan() local
1465 struct platform_device *pdev = info->pdev; in pxa3xx_nand_scan()
1475 if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) in pxa3xx_nand_scan()
1479 info->chunk_size = 512; in pxa3xx_nand_scan()
1481 ret = pxa3xx_nand_sensing(info); in pxa3xx_nand_scan()
1483 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", in pxa3xx_nand_scan()
1484 info->cs); in pxa3xx_nand_scan()
1490 id = *((uint16_t *)(info->data_buff)); in pxa3xx_nand_scan()
1492 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); in pxa3xx_nand_scan()
1494 dev_warn(&info->pdev->dev, in pxa3xx_nand_scan()
1513 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); in pxa3xx_nand_scan()
1518 ret = pxa3xx_nand_config_flash(info, f); in pxa3xx_nand_scan()
1520 dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); in pxa3xx_nand_scan()
1537 if (info->reg_ndcr & NDCR_DWIDTH_M) in pxa3xx_nand_scan()
1541 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_scan()
1542 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_scan()
1564 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { in pxa3xx_nand_scan()
1567 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1587 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, in pxa3xx_nand_scan()
1599 kfree(info->data_buff); in pxa3xx_nand_scan()
1602 info->buf_size = mtd->writesize + mtd->oobsize; in pxa3xx_nand_scan()
1603 ret = pxa3xx_nand_init_buff(info); in pxa3xx_nand_scan()
1606 info->oob_buff = info->data_buff + mtd->writesize; in pxa3xx_nand_scan()
1618 struct pxa3xx_nand_info *info; in alloc_nand_resource() local
1628 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + in alloc_nand_resource()
1630 if (!info) in alloc_nand_resource()
1633 info->pdev = pdev; in alloc_nand_resource()
1634 info->variant = pxa3xx_nand_get_variant(pdev); in alloc_nand_resource()
1636 mtd = (struct mtd_info *)((unsigned int)&info[1] + in alloc_nand_resource()
1640 info->host[cs] = host; in alloc_nand_resource()
1643 host->info_data = info; in alloc_nand_resource()
1649 chip->controller = &info->controller; in alloc_nand_resource()
1662 info->clk = devm_clk_get(&pdev->dev, NULL); in alloc_nand_resource()
1663 if (IS_ERR(info->clk)) { in alloc_nand_resource()
1665 return PTR_ERR(info->clk); in alloc_nand_resource()
1667 ret = clk_prepare_enable(info->clk); in alloc_nand_resource()
1679 info->drcmr_dat = 97; in alloc_nand_resource()
1680 info->drcmr_cmd = 99; in alloc_nand_resource()
1689 info->drcmr_dat = r->start; in alloc_nand_resource()
1698 info->drcmr_cmd = r->start; in alloc_nand_resource()
1710 info->mmio_base = devm_ioremap_resource(&pdev->dev, r); in alloc_nand_resource()
1711 if (IS_ERR(info->mmio_base)) { in alloc_nand_resource()
1712 ret = PTR_ERR(info->mmio_base); in alloc_nand_resource()
1715 info->mmio_phys = r->start; in alloc_nand_resource()
1718 info->buf_size = INIT_BUFFER_SIZE; in alloc_nand_resource()
1719 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in alloc_nand_resource()
1720 if (info->data_buff == NULL) { in alloc_nand_resource()
1726 disable_int(info, NDSR_MASK); in alloc_nand_resource()
1730 pdev->name, info); in alloc_nand_resource()
1736 platform_set_drvdata(pdev, info); in alloc_nand_resource()
1741 free_irq(irq, info); in alloc_nand_resource()
1742 kfree(info->data_buff); in alloc_nand_resource()
1744 clk_disable_unprepare(info->clk); in alloc_nand_resource()
1750 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); in pxa3xx_nand_remove() local
1754 if (!info) in pxa3xx_nand_remove()
1761 free_irq(irq, info); in pxa3xx_nand_remove()
1762 pxa3xx_nand_free_buff(info); in pxa3xx_nand_remove()
1764 clk_disable_unprepare(info->clk); in pxa3xx_nand_remove()
1767 nand_release(info->host[cs]->mtd); in pxa3xx_nand_remove()
1809 struct pxa3xx_nand_info *info; in pxa3xx_nand_probe() local
1835 info = platform_get_drvdata(pdev); in pxa3xx_nand_probe()
1838 struct mtd_info *mtd = info->host[cs]->mtd; in pxa3xx_nand_probe()
1846 info->cs = cs; in pxa3xx_nand_probe()
1873 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); in pxa3xx_nand_suspend() local
1879 if (info->state) { in pxa3xx_nand_suspend()
1880 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); in pxa3xx_nand_suspend()
1885 mtd = info->host[cs]->mtd; in pxa3xx_nand_suspend()
1894 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); in pxa3xx_nand_resume() local
1901 disable_int(info, NDCR_INT_MASK); in pxa3xx_nand_resume()
1908 info->cs = 0xff; in pxa3xx_nand_resume()
1916 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_resume()
1918 mtd = info->host[cs]->mtd; in pxa3xx_nand_resume()